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<html><head><title>1. FOCS 1960: City, State</title><link href="../../../dblp.css" rel="stylesheet" type="text/css" /></head><body> <table width="100%"><tr><td align="left"><a href="../../index.html"><img alt="dblp.uni-trier.de" src="../../Logo.gif" border=0 height=60 width=170></a></td> <td align="right"><a href="http://www.uni-trier.de"><img alt="www.uni-trier.de" src="../../logo_universitaet-trier.gif" border=0 height=48 width=215></a></td></tr></table> <h1>1. <a href="index.html">FOCS</a> 1960</h1> 1st Annual Symposium on Foundations of Computer Science, October 1960. IEEE Computer Society <ul> <li><a name="Calingaert60" href="../../indices/a-tree/c/Calingaert:Peter.html">Peter Calingaert</a>: Switching function canonical forms based on commutative and associative binary operations. 217-224 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Calingaert60">BibTeX</a></font> <li><a name="Elgot60" href="../../indices/a-tree/e/Elgot:Calvin_C=.html">Calvin C. Elgot</a>: Truth functions realizable by single threshold organs. 225-245 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Elgot60">BibTeX</a></font> <li><a name="FrazerM60" href="../../indices/a-tree/f/Frazer:W=_D=.html">W. D. Frazer</a>, <a href="../../indices/a-tree/m/Muller:David_E=.html">David E. Muller</a>: A Method for Factoring the Action of Asynchronous Circuits. 246-249 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/FrazerM60">BibTeX</a></font> <li><a name="Homan60" href="../../indices/a-tree/h/Homan:M=_E=.html">M. E. Homan</a>: A four-megacycle, 24-bit checked binary adder. 250-265 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Homan60">BibTeX</a></font> <li><a name="Ledley60" href="../../indices/a-tree/l/Ledley:Robert_S=.html">Robert S. Ledley</a>: Boolean matrices applied to sequential circuit theory and threshold logics. 266-272 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Ledley60">BibTeX</a></font> <li><a name="Meade60" href="../../indices/a-tree/m/Meade:R=_M=.html">R. M. Meade</a>: Forcing circuitry-Sequential building blocks for logical design. 273-291 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Meade60">BibTeX</a></font> <li><a name="Reinecke60" href="../../indices/a-tree/r/Reinecke_Jr=:Henry.html">Henry Reinecke Jr.</a>: Current-operated diode logic gates. 292-308 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Reinecke60">BibTeX</a></font> <li><a name="Shelly60" href="../../indices/a-tree/s/Shelly:J=_H=.html">J. H. Shelly</a>: The decision and synthesis problems in semimodular switching theory. 309-320 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Shelly60">BibTeX</a></font> <li><a name="Winder60" href="../../indices/a-tree/w/Winder:Robert_O=.html">Robert O. Winder</a>: Single stage threshold logic. 321-332 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Winder60">BibTeX</a></font> </ul><p><div class="footer"> <a href="../../index.html">Home</a> | <a href="../indexa.html">Conferences</a> | <a href="../../journals/index.html">Journals</a> | <a href="../../series/index.html">Series</a> | <a href="../../about/faq.html">FAQ</a> — Search: <a href="http://dblp.l3s.de">Faceted</a> | <a href="http://dblp.mpi-inf.mpg.de/dblp-mirror/index.php">Complete</a> | <a href="../../indices/a-tree/index.html">Author</a></div> <small><a href="../../copyright.html">Copyright ©</a> Sat May 16 23:12:22 2009 by <a href="http://www.informatik.uni-trier.de/~ley/addr.html">Michael Ley</a> (<a href="mailto:ley@uni-trier.de">ley@uni-trier.de</a>)</small></p></body></html>
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