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<html><head><title>4. FOCS 1963: City, State</title><link href="../../../dblp.css" rel="stylesheet" type="text/css" /></head><body> <table width="100%"><tr><td align="left"><a href="../../index.html"><img alt="dblp.uni-trier.de" src="../../Logo.gif" border=0 height=60 width=170></a></td> <td align="right"><a href="http://www.uni-trier.de"><img alt="www.uni-trier.de" src="../../logo_universitaet-trier.gif" border=0 height=48 width=215></a></td></tr></table> <h1>4. <a href="index.html">FOCS</a> 1963</h1> 4th Annual Symposium on Foundations of Computer Science, 1963. IEEE Computer Society <ul> <li><a name="Muller63" href="../../indices/a-tree/m/Muller:David_E=.html">David E. Muller</a>: Infinite sequences and finite machines. 3-16 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Muller63">BibTeX</a></font> <li><a name="ElgotM63" href="../../indices/a-tree/e/Elgot:Calvin_C=.html">Calvin C. Elgot</a>, <a href="../../indices/a-tree/m/Mezei:Jorge_E=.html">Jorge E. Mezei</a>: Two-sided finite-state transductions (abbreviated version). 17-22 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/ElgotM63">BibTeX</a></font> <li><a name="Fischer63" href="../../indices/a-tree/f/Fischer:Patrick_C=.html">Patrick C. Fischer</a>: On computability by certain classes of restricted Turing machines. 23-32 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Fischer63">BibTeX</a></font> <li><a name="Frazer63" href="../../indices/a-tree/f/Frazer:W=_D=.html">W. D. Frazer</a>: Bilateral threshold nets (extended summary). 33-39 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Frazer63">BibTeX</a></font> <li><a name="CoatesL63" href="../../indices/a-tree/c/Coates:C=_L=.html">C. L. Coates</a>, <a href="../../indices/a-tree/l/Lewis_II:Philip_M=.html">Philip M. Lewis II</a>: Threshold gate realizations of logical functions with don't cares. 41-52 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/CoatesL63">BibTeX</a></font> <li><a name="ArnoldL63" href="../../indices/a-tree/a/Arnold:Richard_F=.html">Richard F. Arnold</a>, <a href="../../indices/a-tree/l/Lawler:Eugene_L=.html">Eugene L. Lawler</a>: On the analysis of functional symmetry. 53-62 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/ArnoldL63">BibTeX</a></font> <li><a name="Lawler63" href="../../indices/a-tree/l/Lawler:Eugene_L=.html">Eugene L. Lawler</a>: The minimal synthesis of tree structures. 63-82 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Lawler63">BibTeX</a></font> <li><a name="Levien63" href="../../indices/a-tree/l/Levien:Roger_E=.html">Roger E. Levien</a>: Determining the best ordering of variables in cascade switching circuits. 83-104 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Levien63">BibTeX</a></font> <li><a name="Eichelberger63" href="../../indices/a-tree/e/Eichelberger:Edward_B=.html">Edward B. Eichelberger</a>: Sequential circuit synthesis using input delays. 105-116 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Eichelberger63">BibTeX</a></font> <li><a name="McNaughton63" href="../../indices/a-tree/m/McNaughton:Robert.html">Robert McNaughton</a>: Finite automata and badly timed elements. 117-130 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/McNaughton63">BibTeX</a></font> <li><a name="Booth63" href="../../indices/a-tree/b/Booth:Theodore_M=.html">Theodore M. Booth</a>: Demonstrating hazards in sequential relay circuits. 131-136 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Booth63">BibTeX</a></font> <li><a name="McCluskey63" href="../../indices/a-tree/m/McCluskey:Edward_J=.html">Edward J. McCluskey</a>: Logical design theory of NOR gate networks with no complemented inputs. 137-148 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/McCluskey63">BibTeX</a></font> <li><a name="Miller63" href="../../indices/a-tree/m/Miller:Raymond_E=.html">Raymond E. Miller</a>: A survey of asynchronous logic: Comparing various definitions and models for asynchronous switching circuits. 149-152 <font size="-3"><a href="http://dblp.uni-trier.de/rec/bibtex/conf/focs/Miller63">BibTeX</a></font> </ul><p><div class="footer"> <a href="../../index.html">Home</a> | <a href="../indexa.html">Conferences</a> | <a href="../../journals/index.html">Journals</a> | <a href="../../series/index.html">Series</a> | <a href="../../about/faq.html">FAQ</a> — Search: <a href="http://dblp.l3s.de">Faceted</a> | <a href="http://dblp.mpi-inf.mpg.de/dblp-mirror/index.php">Complete</a> | <a href="../../indices/a-tree/index.html">Author</a></div> <small><a href="../../copyright.html">Copyright ©</a> Sat May 16 23:12:23 2009 by <a href="http://www.informatik.uni-trier.de/~ley/addr.html">Michael Ley</a> (<a href="mailto:ley@uni-trier.de">ley@uni-trier.de</a>)</small></p></body></html>
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