| 2008 |
|---|
| 12 | EE | Zhonghai Lu,
Lei Xia,
Axel Jantsch:
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip.
DDECS 2008: 92-97 |
| 2007 |
|---|
| 11 | EE | Zhonghai Lu,
Ming Liu,
Axel Jantsch:
Layered Switching for Networks on Chip.
DAC 2007: 122-127 |
| 10 | EE | Huimin She,
Zhonghai Lu,
Axel Jantsch,
Li-Rong Zheng,
Dian Zhou:
Traffic Splitting with Network Calculus for Mesh Sensor Networks.
FGCN (2) 2007: 368-373 |
| 9 | EE | Zhonghai Lu,
Axel Jantsch:
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip.
ICCAD 2007: 18-25 |
| 8 | EE | Zhonghai Lu,
Jonas Sicking,
Ingo Sander,
Axel Jantsch:
Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures.
IEEE International Workshop on Rapid System Prototyping 2007: 143-149 |
| 2006 |
|---|
| 7 | EE | Zhonghai Lu,
Mingchen Zhong,
Axel Jantsch:
Evaluation of on-chip networks using deflection routing.
ACM Great Lakes Symposium on VLSI 2006: 296-301 |
| 6 | EE | Zhonghai Lu,
Ingo Sander,
Axel Jantsch:
Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication.
DSD 2006: 37-44 |
| 5 | EE | Zhonghai Lu,
Bei Yin,
Axel Jantsch:
Connection-oriented Multicasting in Wormhole-switched Networks on Chip.
ISVLSI 2006: 205-2110 |
| 2005 |
|---|
| 4 | EE | Zhonghai Lu,
Axel Jantsch,
Ingo Sander:
Feasibility analysis of messages for on-chip networks using wormhole routing.
ASP-DAC 2005: 960-964 |
| 3 | EE | Zhonghai Lu,
Axel Jantsch:
Traffic Configuration for Evaluating Networks on Chips.
IWSOC 2005: 535-540 |
| 2003 |
|---|
| 2 | EE | Ingo Sander,
Axel Jantsch,
Zhonghai Lu:
Development and Application of Design Transformations in ForSyDe.
DATE 2003: 10364-10369 |
| 2002 |
|---|
| 1 | EE | Ingo Sander,
Axel Jantsch,
Zhonghai Lu:
A Case Study of Hardware and Software Synthesis in ForSyDe.
ISSS 2002: 86-91 |
