| 2008 |
|---|
| 11 | EE | Ashoka Visweswara Sathanur,
Antonio Pullini,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Optimal sleep transistor synthesis under timing and area constraints.
ACM Great Lakes Symposium on VLSI 2008: 177-182 |
| 10 | EE | Ashoka Visweswara Sathanur,
Antonio Pullini,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
A Scalable Algorithmic Framework for Row-Based Power-Gating.
DATE 2008: 379-384 |
| 9 | EE | Ashoka Visweswara Sathanur,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction.
ISLPED 2008: 51-56 |
| 8 | EE | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.
Integration 41(1): 2-8 (2008) |
| 2007 |
|---|
| 7 | EE | Andrea Calimera,
Antonio Pullini,
Ashoka Visweswara Sathanur,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.
ACM Great Lakes Symposium on VLSI 2007: 501-504 |
| 6 | EE | Ashoka Visweswara Sathanur,
Andrea Calimera,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.
DATE 2007: 1544-1549 |
| 5 | EE | Karthik Duraisami,
Prassanna Sithambaram,
Ashoka Visweswara Sathanur,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.
ISCAS 2007: 1061-1064 |
| 4 | EE | Ashoka Visweswara Sathanur,
Antonio Pullini,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Timing-driven row-based power gating.
ISLPED 2007: 104-109 |
| 2006 |
|---|
| 3 | EE | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.
ISCAS 2006 |
| 2 | EE | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Dynamic thermal clock skew compensation using tunable delay buffers.
ISLPED 2006: 162-167 |
| 1 | EE | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.
PATMOS 2006: 214-224 |
