ASP-DAC 2002: Bangalore, India

@proceedings{DBLP:conf/aspdac/2002,
  title     = {Proceedings of the ASPDAC 2002 / VLSI Design 2002, CD-ROM, 7-11
               January 2002, Bangalore, India},
  booktitle = {ASP-DAC},
  publisher = {IEEE},
  year      = {2002},
  isbn      = {0-7695-1299-2},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

• Biswadip Mitra:
  Consumer Digitization: Accelerating DSP Applications, Growing VLSI Design Challenges. 3-4
  Electronic Edition (ACM DL) BibTeX
• Kazuo Yano:
  LSI Design in the 21st Century: Key Changes in Sub-1V Giga-Integration Era. 5
  Electronic Edition (ACM DL) BibTeX
• Aart J. de Geus:
  Electronic Industry on Fire: How to Survive and Thrive. 6
  Electronic Edition (ACM DL) BibTeX
• Martin F. H. Schuurmans:
  Digital Watermarking. 7-10
  Electronic Edition (ACM DL) BibTeX
• Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan:
  Functional Verification of System on Chips-Practices, Issues and Challenges. 11-13
  Electronic Edition (ACM DL) BibTeX
• Pieter van der Wolf, W. M. Kruijtzer, Jos T. J. van Eijndhoven:
  T2: System-Level Design of Embedded Media Systems. 14-15
  Electronic Edition (ACM DL) BibTeX
• Stefan Rusu, Manoj Sachdev, Christer Svensson, B. Nauta:
  T3: Trends and Challenges in VLSI Technology Scaling towards 100nm. 16-17
  Electronic Edition (ACM DL) BibTeX
• M. V. Atre, P. S. Subramanian, H. Narayanan:
  T4: Mathematical Methods in VLSI. 18-19
  Electronic Edition (ACM DL) BibTeX
• Vishwani D. Agrawal, Michael L. Bushnell:
  T5: Electronic Testing for SOC Designers. 20
  Electronic Edition (ACM DL) BibTeX
• Luciano Lavagno, Sujit Dey, Rajesh Gupta:
  Specification, Modeling and Design Tools for System-on-Chip. 21-23
  Electronic Edition (ACM DL) BibTeX
• R. Lal, P. R. Apte, K. N. Bhat, G. Bose, S. Chandra, D. K. Sharma:
  T7: MEMS: Technology, Design, CAD and Applications. 24-25
  Electronic Edition (ACM DL) BibTeX
• Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside:
  T8: Logic Design of Asynchronous Circuits. 26-30
  Electronic Edition (ACM DL) BibTeX
• David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin:
  Evaluating Run-Time Techniques for Leakage Power Reduction. 31-38
  Electronic Edition (ACM DL) BibTeX
• Wenjie Jiang, Vivek Tiwari, Erik de la Iglesia, Amit Sinha:
  Topological Analysis for Leakage Prediction of Digital Circuits. 39-44
  Electronic Edition (ACM DL) BibTeX
• Rahul Kumar, C. P. Ravikumar:
  Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment. 45-50
  Electronic Edition (ACM DL) BibTeX
• Fei Li, Lei He, Kewal K. Saluja:
  Estimation of Maximum Power-up Current. 51-58
  Electronic Edition (ACM DL) BibTeX
• Joong-Ho Kim, Erdem Matoglu, Jinwoo Choi, Madhavan Swaminathan:
  Modeling of Multi-Layered Power Distribution Planes Including Via Effects Using Transmission Matrix Method. 59-64
  Electronic Edition (ACM DL) BibTeX
• Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy:
  Dynamic Noise Analysis with Capacitive and Inductive Coupling. 65-70
  Electronic Edition (ACM DL) BibTeX
• Makoto Nagata, Youichi Nishimori, Takashi Morie, Atsushi Iwata, Yoshitaka Murasaka:
  Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. 71-76
  Electronic Edition (ACM DL) BibTeX
• Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu:
  Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. 77-86
  Electronic Edition (ACM DL) BibTeX
• Rupesh S. Shelar, Sachin S. Sapatnekar:
  An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. 87-92
  Electronic Edition (ACM DL) BibTeX
• Hiroshi Saito, Takashi Nanya, Alex Kondratyev:
  Design of Asynchronous Controllers with Delay Insensitive Interface. 93-98
  Electronic Edition (ACM DL) BibTeX
• Debasis Samanta, Ajit Pal, Nishant Sinha:
  Synthesis of High Performance Low Power Dynamic CMOS Circuits. 99-104
  Electronic Edition (ACM DL) BibTeX
• Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri:
  Improvement of ASIC Design Processes. 105-112
  Electronic Edition (ACM DL) BibTeX
• Haris Lekatsas, Jörg Henkel:
  ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs. 113-120
  Electronic Edition (ACM DL) BibTeX
• Rung-Bin Lin, Chi-Ming Tsai:
  Weight-Based Bus-Invert Coding for Low-Power Applications. 121-125
  Electronic Edition (ACM DL) BibTeX
• Wei-Chung Cheng, Jian-Lin Liang, Massoud Pedram:
  Software-Only Bus Encoding Techniques for an Embedded System. 126-131
  Electronic Edition (ACM DL) BibTeX
• Payam Heydari, Massoud Pedram:
  Interconnect Energy Dissipation in High-Speed ULSI Circuits. 132-140
  Electronic Edition (ACM DL) BibTeX
• N. S. Nagaraj, Poras T. Balsara, Cyrus Cantrell:
  Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. 141
  Electronic Edition (ACM DL) BibTeX
• P. K. Datta, S. Sanyal, D. Bhattacharya:
  Losses in Multilevel Crossover in VLSI Interconnects. 142-146
  Electronic Edition (ACM DL) BibTeX
• Qinwei Xu, Pinaki Mazumder:
  Rational ABCD Modeling of High-Speed Interconnects. 147-154
  Electronic Edition (ACM DL) BibTeX
• Kuo-Hsing Cheng, Shun-Wen Cheng:
  Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. 155-159
  Electronic Edition (ACM DL) BibTeX
• Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
  A New Synthesis of Symmetric Functions. 160-165
  Electronic Edition (ACM DL) BibTeX
• Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada:
  Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. 166-171
  Electronic Edition (ACM DL) BibTeX
• D. Sarkar:
  Register Transfer Operation Analysis during Data Path Verification. 172-180
  Electronic Edition (ACM DL) BibTeX
• Ashok K. Murugavel, N. Ranganathan:
  A Real Delay Switching Activity Simulator based on Petri net Modeling. 181-186
  Electronic Edition (ACM DL) BibTeX
• Sanjukta Bhanja, N. Ranganathan:
  Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. 187-192
  Electronic Edition (ACM DL) BibTeX
• Debasis Samanta, Ajit Pal:
  Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. 193-198
  Electronic Edition (ACM DL) BibTeX
• Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti:
  Minimizing Energy Consumption for High-Performance Processing. 199-206
  Electronic Edition (ACM DL) BibTeX
• A. B. Bhattacharyya, Shrutin Ulman:
  PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis. 207-212
  Electronic Edition (ACM DL) BibTeX
• Peter M. Lee, Shinji Ito, Takeaki Hashimoto, Tomomasa Touma, Junji Sato, Goichi Yokomizo:
  A Parallel and Accelerated Circuit Simulator with Precise Accuracy. 213-218
  Electronic Edition (ACM DL) BibTeX
• Srinath R. Naidu:
  Timing Yield Calculation Using an Impulse-train Approach. 219-224
  Electronic Edition (ACM DL) BibTeX
• H. C. Srinivasaiah, Navakanta Bhat:
  Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. 225-232
  Electronic Edition (ACM DL) BibTeX
• Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar:
  Exploring the Number of Register Windows in ASIP Synthesis. 233-238
  Electronic Edition (ACM DL) BibTeX
• Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr:
  Architecture Implementation Using the Machine Description Language LISA. 239-244
  Electronic Edition (ACM DL) BibTeX
• Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
  A Framework for Design Space Exploration of Parameterized VLSI Systems. 245-250
  Electronic Edition (ACM DL) BibTeX
• S. Chakraverty, C. P. Ravikumar, D. Roy Choudhuri:
  An Evolutionary Scheme for Cosynthesis of Real-Time Systems. 251-260
  Electronic Edition (ACM DL) BibTeX
• Kanishka Lahiri, Sujit Dey, Debashis Panigrahi, Anand Raghunathan:
  Battery-Driven System Design: A New Frontier in Low Power Design. 261-267
  Electronic Edition (ACM DL) BibTeX
• Masanori Muroyama, Akihiko Hyodo, Hiroto Yasuura, Tohru Ishihara:
  A Power Minimization Technique for Arithmetic Circuits by Cell Selection. 268-273
  Electronic Edition (ACM DL) BibTeX
• Yunsi Fei, Niraj K. Jha:
  Functional Partitioning for Low Power Distributed Systems of Systems-on-a-chip. 274-281
  Electronic Edition (ACM DL) BibTeX
• Tohru Ishihara, Kunihiro Asada:
  An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. 282-287
  Electronic Edition (ACM DL) BibTeX
• Victor M. DeLaLuz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, Ibrahim Kolcu:
  Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories. 288-296
  Electronic Edition (ACM DL) BibTeX
• S. Natarajan, A. Marshall:
  Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI. 297-298
  Electronic Edition (ACM DL) BibTeX
• Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R. Suresh:
  Transistor Flaring in Deep Submicron-Design Considerations. 299-304
  Electronic Edition (ACM DL) BibTeX
• Shuzhou Fang, Zeyi Wang, Xianlong Hong:
  A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. 305-310
  Electronic Edition (ACM DL) BibTeX
• Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh:
  Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. 311-316
  Electronic Edition (ACM DL) BibTeX
• Maryam Shojaei Baghini, Madhav P. Desai:
  Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches. 317-324
  Electronic Edition (ACM DL) BibTeX
• P. Klapproth:
  Embedded Tutorial: General Architectural Concepts for IP Core Re-Use. 325
  Electronic Edition (ACM DL) BibTeX
• Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri:
  Framework for Synthesis of Virtual Pipelines. 326-331
  Electronic Edition (ACM DL) BibTeX
• Junyu Peng, Samar Abdi, Daniel Gajski:
  Automatic Model Refinement for Fast Architecture Exploration. 332-337
  Electronic Edition (ACM DL) BibTeX
• Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck, K. U. Leuven:
  Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. 338-344
  Electronic Edition (ACM DL) BibTeX
• Li Shang, Niraj K. Jha:
  Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs. 345-354
  Electronic Edition (ACM DL) BibTeX
• Takayuki Sugawara, Yoshikazu Miyanaga, Norinobu Yoshida:
  A Design of Analog C-Matrix Circuits used for Signal/Data Processing. 355-359
  Electronic Edition (ACM DL) BibTeX
• Debapriya Sahu:
  A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment. 360-365
  Electronic Edition (ACM DL) BibTeX
• Biranchinath Sahu, Aloke K. Dutta:
  Automatic Synthesis of CMOS Operational Amplifiers: A Fuzzy Optimization Approach. 366-371
  Electronic Edition (ACM DL) BibTeX
• Jens Lienig, Goeran Jerke, Thorsten Adler:
  Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing. 372-380
  Electronic Edition (ACM DL) BibTeX
• Wei Chen, Massoud Pedram, Premal Buch:
  Buffered Routing Tree Construction Under Buffer Placement Blockages. 381-386
  Electronic Edition (ACM DL) BibTeX
• Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
  Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. 387-392
  Electronic Edition (ACM DL) BibTeX
• Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin:
  An Adaptive Interconnect-Length Driven Placer. 393-398
  Electronic Edition (ACM DL) BibTeX
• Stelian Alupoaei, Srinivas Katkoori:
  Net Clustering Based Macrocell Placement. 399-406
  Electronic Edition (ACM DL) BibTeX
• Vijay Raghunathan, Mani B. Srivastava, Milos D. Ercegovac, Anand Raghunathan:
  High-Level Synthesis with SIMD Units. 407-413
  Electronic Edition (ACM DL) BibTeX
• J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahmut T. Kandemir:
  A Heuristic for Clock Selection in High-Level Synthesis. 414-419
  Electronic Edition (ACM DL) BibTeX
• Indradeep Ghosh, Krishna Sekar, Vamsi Boppana:
  Design for Verification at the Register Transfer Level. 420-425
  Electronic Edition (ACM DL) BibTeX
• Gabriela Nicolescu, S. Martinez, Lobna Kriaa, Wassim Youssef, Sungjoo Yoo, Benoît Charlot, Ahmed Amine Jerraya:
  Application of Multi-domain and Multi-language Cosimulation To an Optical MEM Switch Design. 426-434
  Electronic Edition (ACM DL) BibTeX
• Kavish Seth, S. Srinivasan:
  VLSI Implementation of 2-D DWT/IDWT Cores using 9/7-tap filter banks based on the Non-expansive Symmetric Extension Scheme. 435-440
  Electronic Edition (ACM DL) BibTeX
• Hak-soo Yu, Jacob A. Abraham:
  An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation. 441-446
  Electronic Edition (ACM DL) BibTeX
• Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka Phani, Ansuman Rout:
  Architecture and Design of a High Performance SRAM for SoC Design. 447-451
  Electronic Edition (ACM DL) BibTeX
• Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
  VLSI Architecture for a Flexible Motion Estimation with Parameters. 452-457
  Electronic Edition (ACM DL) BibTeX
• Prabhat Mishra, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama:
  Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language. 458-466
  Electronic Edition (ACM DL) BibTeX
• Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita:
  Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. 467-472
  Electronic Edition (ACM DL) BibTeX
• Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
  An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. 473-478
  Electronic Edition (ACM DL) BibTeX
• Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita:
  Simultaneous Circuit Transformation and Routing. 479-483
  Electronic Edition (ACM DL) BibTeX
• Chunhong Chen:
  Probabilistic Analysis of Rectilinear Steiner Trees. 484-488
  Electronic Edition (ACM DL) BibTeX
• Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
  Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. 489-498
  Electronic Edition (ACM DL) BibTeX
• Hailong Cui, Sharad C. Seth, Shashank K. Mehta:
  A Novel Method to Improve the Test Efficiency of VLSI Tests. 499-504
  Electronic Edition (ACM DL) BibTeX
• Sandeep Koranne:
  On Test Scheduling for Core-Based SOCs. 505-510
  Electronic Edition (ACM DL) BibTeX
• Yu Huang, Sudhakar M. Reddy, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng:
  Constraint Driven Pin Mapping for Concurrent SOC Testing. 511-516
  Electronic Edition (ACM DL) BibTeX
• Katarzyna Radecka, Zeljko Zilic:
  Identifying Redundant Wire Replacements for Synthesis and Verification. 517-523
  Electronic Edition (ACM DL) BibTeX
• Aarti Gupta, Albert E. Casavant, Pranav Ashar, Akira Mukaiyama, Kazutoshi Wakabayashi, X. G. Liu:
  Property-Specific Testbench Generation for Guided Simulation. 524-534
  Electronic Edition (ACM DL) BibTeX
• Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan:
  A New Divide and Conquer Method for Achieving High Speed Division in Hardware. 535-540
  Electronic Edition (ACM DL) BibTeX
• Tony Han, Sri Parameswaran:
  Swasad: An Asic Design For High Speed Dna Sequence Matching. 541-546
  Electronic Edition (ACM DL) BibTeX
• Martin Palkovic, Miguel Miranda, Kristof Denolf, Peter Vos, Francky Catthoor:
  Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder. 547-552
  Electronic Edition (ACM DL) BibTeX
• Debashis Panigrahi, Clark N. Taylor, Sujit Dey:
  A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication. 553-560
  Electronic Edition (ACM DL) BibTeX
• Qinwei Xu, Pinaki Mazumder:
  Efficient Macromodeling for On-Chip Interconnects. 561-566
  Electronic Edition (ACM DL) BibTeX
• Silke Salewski, Erich Barke:
  An Upper Bound for 3D Slicing Floorplans. 567-572
  Electronic Edition (ACM DL) BibTeX
• Jingcao Hu, Yangdong Deng, Radu Marculescu:
  System-Level Point-to-Point Communication Synthesis Using Floorplanning Information. 573-579
  Electronic Edition (ACM DL) BibTeX
• Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky:
  Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. 580-591
  Electronic Edition (ACM DL) BibTeX
• Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal:
  Multiple Faults: Modeling, Simulation and Test. 592-597
  Electronic Edition (ACM DL) BibTeX
• Subhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik:
  Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch. 598-603
  Electronic Edition (ACM DL) BibTeX
• Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski:
  Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. 604-614
  Electronic Edition (ACM DL) BibTeX
• Sornavalli Ramanathan, Rituparna Mandal:
  Low Power Solution for Wireless Applications. 615-618
  Electronic Edition (ACM DL) BibTeX
• J. Ramanujam, Satish Krishnamurthy, Jinpyo Hong, Mahmut T. Kandemir:
  Address Code and Arithmetic Optimizations for Embedded Systems. 619-624
  Electronic Edition (ACM DL) BibTeX
• Yong-Ha Park, Hoi-Jun Yoo, Jeonghoon Kook:
  Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-chip (SoC) Applications. 625-630
  Electronic Edition (ACM DL) BibTeX
• N. E. Crosbie, Mahmut T. Kandemir, Ibrahim Kolcu, J. Ramanujam, Alok N. Choudhary:
  Strategies for Improving Data Locality in Embedded Applications. 631-638
  Electronic Edition (ACM DL) BibTeX
• Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia:
  On Routing Demand and Congestion Estimation for FPGAs. 639-646
  Electronic Edition (ACM DL) BibTeX
• Supratik Chakraborty, Rajeev Murgai:
  Layout-driven Timing Optimization by Generalized De Morgan Transform. 647-654
  Electronic Edition (ACM DL) BibTeX
• Rituparna Mandal, Dibyendu Goswami, Arup Dash:
  Reducing Library Development Cycle Time through an Optimum Layout Create Flow. 655-660
  Electronic Edition (ACM DL) BibTeX
• Evangeline F. Y. Young, M. L. Ho, Chris C. N. Chu:
  A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. 661-670
  Electronic Edition (ACM DL) BibTeX
• Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das:
  Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. 671-676
  Electronic Edition (ACM DL) BibTeX
• Irith Pomeranz, Sudhakar M. Reddy:
  A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. 677-682
  Electronic Edition (ACM DL) BibTeX
• Makoto Sugihara, Hiroto Yasuura:
  Optimization of Test Accesses with a Combined BIST and External Test Scheme. 683-688
  Electronic Edition (ACM DL) BibTeX
• Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri:
  Design of An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS). 689-696
  Electronic Edition (ACM DL) BibTeX
• Dexin Li, Pai H. Chou, Nader Bagherzadeh:
  Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems. 697-704
  Electronic Edition (ACM DL) BibTeX
• Anupam Datta, Sidharth Choudhury, Anupam Basu:
  Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks. 705-710
  Electronic Edition (ACM DL) BibTeX
• Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
  Input Space Adaptive Embedded Software Synthesis. 711-718
  Electronic Edition (ACM DL) BibTeX
• Jiong Luo, Niraj K. Jha:
  Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. 719-728
  Electronic Edition (ACM DL) BibTeX
• Malay K. Ganai, Adnan Aziz:
  Improved SAT-based Bounded Reachability Analysis. 729-734
  Electronic Edition (ACM DL) BibTeX
• Pallab Dasgupta, Arindam Chakrabarti, P. P. Chakrabarti:
  Open Computation Tree Logic for Formal Verification of Modules. 735-740
  Electronic Edition (ACM DL) BibTeX
• Raik Brinkmann, Rolf Drechsler:
  RTL-Datapath Verification using Integer Linear Programming. 741-746
  Electronic Edition (ACM DL) BibTeX
• Rajarshi Mukherjee, Yozo Nakayama, Toshiya Mima:
  Verification of an Industrial CC-NUMA Server. 747-754
  Electronic Edition (ACM DL) BibTeX
• Sagar S. Sabade, Hank Walker:
  Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. 755-760
  Electronic Edition (ACM DL) BibTeX
• C. P. Ravikumar, Rahul Kumar:
  Divide-and-Conquer IDDQ Testing for Core-based System Chips. 761-766
  Electronic Edition (ACM DL) BibTeX
• Yun Shao, Sudhakar M. Reddy, Irith Pomeranz:
  Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. 767-772
  Electronic Edition (ACM DL) BibTeX
• Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi:
  Test Solution For OTA Based Analog Circuits. 773-788
  Electronic Edition (ACM DL) BibTeX
• Sanjeev Patel:
  Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study. 789-794
  Electronic Edition (ACM DL) BibTeX
• Ranjit Yashwante, Bhalchandra Jahagirdar:
  IEEE 1394a_2000 Physical Layer ASIC. 795-800
  Electronic Edition (ACM DL) BibTeX
• T. Datta, C. S. Muralidharan:
  Definition, Design and Development of the IXE2424 Network Switch/Router ASIC. 801
  Electronic Edition (ACM DL) BibTeX