12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India.
IEEE Computer Society 1999 BibTeX
Invited Talks
- Robert A. Pease:
Invited Talk: The Information Appliance and Its Interface to the Analog World: Easy - Or Not So Easy.
BibTeX
TCAD to ECAD I
- Nagaraj Ns, Poras T. Balsara, Cyrus Cantrell:
Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis.
6-11 BibTeX
- Li-Fu Chang, Abhay Dubey, Keh-Jeng Chang, Robert Mathews, Ken Wong:
Incorporating Process Induced Effects into RC Extraction.
12-17 BibTeX
- Marko P. Chew, Sharad Saxena, Thomas F. Cobourn, Purnendu K. Mozumder, Andrzej J. Strojwas:
A New Methodology for Concurrent Technology Development and Cell Library Optimization.
18-25
Electronic Edition (link) BibTeX
Low Power I
- Bedabrata Pain, Guang Yang, Brita Olson, Timothy Shaw, Monico Ortiz, Julie Heynssens, Chris Wrigley, Charlie Ho:
A Low-Power Digital Camera-on-a-Chip Implemented in CMOS Active Pixel Approach.
26-31
Electronic Edition (link) BibTeX
- Anantha Chandrakasan, Abram P. Dancy, James Goodman, Thomas Simon:
A Low-Power Wireless Camera System.
32-36 BibTeX
- Paulo F. Flores, José C. Costa, Horácio C. Neto, José C. Monteiro, João P. Marques Silva:
Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation.
37-41
Electronic Edition (link) BibTeX
- Mahesh Mehendale, Sunil D. Sherlekar:
Low Power Code Generation of Multiplication-free Linear Transforms.
42-47 BibTeX
- Nithya Raghavan, Venkatesh Akella, Smita Bakshi:
Automatic Insertion of Gated Clocks at Register Transfer Level.
48-54
Electronic Edition (link) BibTeX
- Kavita Nair, Ramesh Harjani:
Compact, Ultra Low Power, Programmable Continuous-Time Filter Banks for Feedback Cancellation in Hearing Aid.
55-60
Electronic Edition (link) BibTeX
- P. K. Singh, Sriram Jayasimha:
A Low-Complexity, Reduced-Power Viterbi Algorithm.
61-66 BibTeX
- Basabi Bhaumik, Pravas Pradhan, G. S. Visweswaran, Rajamohan Varambally, Anand Hardi:
A Low Power 256 KB SRAM Design.
67-71 BibTeX
Testing I
TCAD to ECAD II
Co-Design and Synthesis
Analog Design I
Multi-Valued Logic
Verification I
Testing II
- Irith Pomeranz, Sudhakar M. Reddy:
VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits.
250-255
Electronic Edition (link) BibTeX
- Pradip A. Thaker, Mona E. Zaghloul, Minesh B. Amin:
Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations.
256-259
Electronic Edition (link) BibTeX
- Zbigniew Kalbarczyk, Janak H. Patel, Myeong S. Lee, Ravishankar K. Iyer:
An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits.
260-265 BibTeX
- Debaleena Das, Nur A. Touba:
A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems.
266-269
Electronic Edition (link) BibTeX
- Bernard Courtois, Jean-Michel Karam, Salvador Mir, Marcelo Lubaszewski, Vladimir Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner:
Design and Test of MEMs.
270- BibTeX
Verification II
- Vishnu A. Patankar, Alok Jain, Randal E. Bryant:
Formal Verification of an ARM Processor.
282-287
Electronic Edition (link) BibTeX
- Srivatsan Srinivasan, Parminder Singh Chhabra, Praveen Kumar Jaini, Adnan Aziz, Lizy Kurian John:
Formal Verification of a Snoop-Based Cache Coherence Protocol Using Symbolic Model Checking.
288-293
Electronic Edition (link) BibTeX
- Jatindra Kumar Deka, Pallab Dasgupta, P. P. Chakrabarti:
An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays.
294-299
Electronic Edition (link) BibTeX
- Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen:
Superscalar Processor Validation at the Microarchitecture Level.
300-305
Electronic Edition (link) BibTeX
- Tamarah Arons, Amir Pnueli:
Verifying Tomasulo's Algoithm by Refinement.
306-309
Electronic Edition (link) BibTeX
- Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman:
Logic Verification of Very Large Circuits Using Shark.
310-317
Electronic Edition (link) BibTeX
- Ingo Sander, Axel Jantsch:
Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons.
318-323 BibTeX
- Pankaj Chauhan, Pallab Dasgupta, P. P. Chakrabarti:
Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams.
324-
Electronic Edition (link) BibTeX
DSP
- Anupam Basu, Rainer Leupers, Peter Marwedel:
Array Index Allocation under Register Constraints in DSP Programs.
330-335 BibTeX
- D. V. R. Murthy, S. Ramachandran, S. Srinivasan:
Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs.
336-339
Electronic Edition (link) BibTeX
- Bupesh Pandita, Subir K. Roy:
Design and Implementation of Viterbi Decoder Using FPGAs.
611-
Electronic Edition (link) BibTeX
- M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale:
Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms.
340-345
Electronic Edition (link) BibTeX
- Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar:
A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors.
346-349
Electronic Edition (link) BibTeX
- S. Ramanathan, V. Visvanathan, S. K. Nandy:
Synthesis of Configurable Architectures for DSP Algorithms.
350-357
Electronic Edition (link) BibTeX
- Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag:
Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures.
358-
Electronic Edition (link) BibTeX
Logic Synthesis
- Peichen Pan, Guohua Chen:
Optimal Retiming for Initial State Computation.
366-371
Electronic Edition (link) BibTeX
- Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns:
Performance Driven Synthesis for Pass-Transistor Logic.
372-377 BibTeX
- B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai:
A State Assignment Scheme Targeting Performance and Area.
378-383
Electronic Edition (link) BibTeX
- S. Ramesh:
Efficient Translation of Statecharts to Hardware Circuits.
384-389
Electronic Edition (link) BibTeX
- Chitrasena Bhat, Niranjan N. Chiplunkar:
Heuristic Technology Mapper For Lut Based Fpgas.
390-393
Electronic Edition (link) BibTeX
- Rajeev Murgai, Jawahar Jain, Masahiro Fujita:
Efficient Scheduling Techniques for ROBDD Construction.
394-401
Electronic Edition (link) BibTeX
- Prashant Saxena, Peichen Pan, C. L. Liu:
The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches.
402-407
Electronic Edition (link) BibTeX
- Amit Narayon:
Recent Advances in BDD Based Representations for Boolean Functions: A Survey.
408-
Electronic Edition (link) BibTeX
Low Power II
- Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik:
POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing.
416-422 BibTeX
- Pradeep Prabhakaran, Prithviraj Banerjee, Jim E. Crenshaw, Majid Sarrafzadeh:
Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization.
423-427
Electronic Edition (link) BibTeX
- Mircea R. Stan:
Optimal Voltages and Sizing for Low Power.
428-433
Electronic Edition (link) BibTeX
- Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss:
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method.
434-439
Electronic Edition (link) BibTeX
- Unni Narayanan, Georgios I. Stamoulis, Rabindra K. Roy:
Characterizing Individual Gate Power Sensitivity in Low Power Design.
625- BibTeX
- Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan:
Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages.
440-
Electronic Edition (link) BibTeX
Physical Design I
- Bulent Basaran, Kiran Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, Srinivasan Rangarajan, Naresh Sehgal:
GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs.
448-452
Electronic Edition (link) BibTeX
- Avaneendra Gupta, John P. Hayes:
Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells.
453-459
Electronic Edition (link) BibTeX
- C. S. Raghu, Suravi Bhowmik, Poorvaja Ramani, S. Sundaram:
COST Circuit Optimization SysTem in ASIC Library Development Environment.
460-463
Electronic Edition (link) BibTeX
- Andrew B. Kahng, Sudhakar Muddu, Egino Sarto:
Interconnect Optimization Strategies for High-Performance VLSI Designs.
464-469 BibTeX
- Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang:
Modeling Crosstalk in Resistive VLSI Interconnections.
470-475
Electronic Edition (link) BibTeX
- Noel Menezes, Chung-Ping Chen:
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect.
476-
Electronic Edition (link) BibTeX
Testing III
- Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
A Test Generator for Segment Delay Faults.
484-491
Electronic Edition (link) BibTeX
- Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell:
A Complete Characterization of Path Delay Faults through Stuck-at Faults.
492-497
Electronic Edition (link) BibTeX
- Jue Wu, Elizabeth M. Rudnick:
A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults.
498-505
Electronic Edition (link) BibTeX
- Shashank K. Mehta, Sharad C. Seth:
Empirical Computation of Reject Ratio in VLSI Testing.
506-511
Electronic Edition (link) BibTeX
- Susanta Chakraborty, Sandip Das, Debesh K. Das, Bhargab B. Bhattacharya:
Synthesis of Symmetric Functions for Path-Delay Fault Testability.
512-517
Electronic Edition (link) BibTeX
- Sudip Chakrabarti, Abhijit Chatterjee:
Diagnostic Test Pattern Generation for Analog Circuits Using Hierarchical Models.
518-523
Electronic Edition (link) BibTeX
Digital Design and Applications
- Rajiv V. Joshi, Wei Hwang:
Design Considerations and Implementation of a High Performance Dynamic Register File.
526-531
Electronic Edition (link) BibTeX
- Kolin Paul, P. Dutta, Dipanwita Roy Chowdhury, Prasanta Kumar Nandi, Parimal Pal Chaudhuri:
A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata.
532-537 BibTeX
- Jacob Augustine, William E. Lynch, Yuke Wang, Asim J. Al-Khalili:
Lossy Compression of Images Using Logic Minimization.
538-543
Electronic Edition (link) BibTeX
- Swarup Bhunia, Soumya K. Ghosh, Pramod Kumar, Partha Pratim Das, Jayanta Mukherjee:
Design, Simulation and Synthesis of an ASIC for Fractal Image Compression.
544-547
Electronic Edition (link) BibTeX
- Lov K. Grover:
Invited Talk: Quantum Computation.
548- BibTeX
Physical Design II
Analog Design II
Tutorials
- Srinivas Devadas, Sharad Malik, José C. Monteiro, Luciano Lavagno:
CAD Techniques for Embedded System Design.
608 BibTeX
- Manuel d'Arbreu, Abhijit Chatterjee:
Manufacturability of Mixed Signal Systems.
608 BibTeX
- Kaushik Roy, Anand Raghunathan, Sujit Dey:
Low Power Design Methodologies for Systems-on-Chips.
609 BibTeX
- Rahul Razdan, Apurva Kalia, Manu Lauria:
Verification of Systems-on-Chip Designs.
609 BibTeX
- Sudip Nag, H. K. Verma, Kaushik Roy:
VLSI Signal Processing in FPGAs.
609 BibTeX
- Janusz Rajski, Jerzy Tyszer, Sanjay Patel:
Built-In Self-Test for Systems on Silicon.
609-610 BibTeX
Copyright © Tue May 27 18:17:02 2008
by Michael Ley (ley@uni-trier.de)
