| 2008 |
|---|
| 66 | EE | I-De Huang,
Yi-Shing Chang,
Sandeep K. Gupta,
Sreejit Chakravarty:
An Industrial Case Study of Sticky Path-Delay Faults.
VTS 2008: 395-402 |
| 65 | EE | Fan Yang,
Sreejit Chakravarty,
Narendra Devta-Prasanna,
Sudhakar M. Reddy,
Irith Pomeranz:
On the Detectability of Scan Chain Internal Faults — An Industrial Case Study.
VTS 2008: 79-84 |
| 2006 |
|---|
| 64 | EE | Abhijit Jas,
Yi-Shing Chang,
Sreejit Chakravarty:
An Approach to Minimizing Functional Constraints.
DFT 2006: 215-226 |
| 63 | EE | Suriyaprakash Natarajan,
Srinivas Patil,
Sreejit Chakravarty:
Path Delay Fault Simulation on Large Industrial Designs.
VTS 2006: 16-23 |
| 62 | EE | Eric N. Tran,
Vishwashanth Kasulasrinivas,
Sreejit Chakravarty:
Silicon Evaluation of Logic Proximity Bridge Patterns.
VTS 2006: 78-85 |
| 61 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas,
Sreejit Chakravarty,
Rathish Jayabharathi:
Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2954-2964 (2006) |
| 2005 |
|---|
| 60 | EE | Sreejit Chakravarty:
Improving Logic Test Quality of Microprocessors.
Asian Test Symposium 2005 |
| 59 | EE | Manan Syal,
Michael S. Hsiao,
Suriyaprakash Natarajan,
Sreejit Chakravarty:
Untestable Multi-Cycle Path Delay Faults in Industrial Designs.
Asian Test Symposium 2005: 194-201 |
| 58 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas,
Sreejit Chakravarty,
Rathish Jayabharathi:
Implicit and Exact Path Delay Fault Grading in Sequential Circuits.
DATE 2005: 990-995 |
| 57 | EE | Yi-Shing Chang,
Sreejit Chakravarty,
Hiep Hoang,
Nick Thorpe,
Khen Wee:
Transition Tests for High Performance Microprocessors.
VTS 2005: 29-34 |
| 56 | EE | Sreejit Chakravarty,
Yi-Shing Chang,
Hiep Hoang,
Sridhar Jayaraman,
Silvio Picano,
Cheryl Prunty,
Eric W. Savage,
Rehan Sheikh,
Eric N. Tran,
Khen Wee:
Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor.
VTS 2005: 337-342 |
| 55 | EE | Xiao Liu,
Michael S. Hsiao,
Sreejit Chakravarty,
Paul J. Thadikaran:
Efficient techniques for transition testing.
ACM Trans. Design Autom. Electr. Syst. 10(2): 258-278 (2005) |
| 2004 |
|---|
| 54 | EE | Manan Syal,
Michael S. Hsiao,
Sreejit Chakravarty:
Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks.
ITC 2004: 1034-1043 |
| 53 | EE | Sreejit Chakravarty,
Eric W. Savage,
Eric N. Tran:
Defect Coverage Analysis of Partitioned Testing.
ITC 2004: 907-915 |
| 52 | EE | Sujit T. Zachariah,
Sreejit Chakravarty:
Extraction of two-node bridges from large industrial circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 433-439 (2004) |
| 2003 |
|---|
| 51 | EE | Manan Syal,
Michael S. Hsiao,
Kiran B. Doreswamy,
Sreejit Chakravarty:
Efficient Implication - Based Untestable Bridge Fault Identifier.
VTS 2003: 393-402 |
| 50 | EE | Sujit T. Zachariah,
Sreejit Chakravarty:
Algorithm to extract two-node bridges.
IEEE Trans. VLSI Syst. 11(4): 741-744 (2003) |
| 2002 |
|---|
| 49 | EE | Sreejit Chakravarty:
Supplemental Test Methods (Tutorial Abstract).
ISQED 2002: 7 |
| 48 | EE | Sreejit Chakravarty,
Ankur Jain,
Nandakumar Radhakrishnan,
Eric W. Savage,
Sujit T. Zachariah:
Experimental Evaluation of Scan Tests for Bridges.
ITC 2002: 509-518 |
| 47 | EE | Xiao Liu,
Michael S. Hsiao,
Sreejit Chakravarty,
Paul J. Thadikaran:
Techniques to Reduce Data Volume and Application Time for Transition Test.
ITC 2002: 983-992 |
| 46 | EE | Sreejit Chakravarty,
Kambiz Komeyli,
Eric W. Savage,
Michael J. Carruthers,
Bret T. Stastny,
Sujit T. Zachariah:
Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms.
VTS 2002: 367-372 |
| 45 | EE | Sreejit Chakravarty,
Ankur Jain:
Fault Models for Speed Failures Caused by Bridges and Opens.
VTS 2002: 373-378 |
| 2001 |
|---|
| 44 | EE | Sujit T. Zachariah,
Sreejit Chakravarty:
A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits.
VLSI Design 2001: 333-338 |
| 43 | EE | Ismed Hartanto,
Srikanth Venkataraman,
W. Kent Fuchs,
Elizabeth M. Rudnick,
Janak H. Patel,
Sreejit Chakravarty:
Diagnostic simulation of stuck-at faults in sequential circuits using compact lists.
ACM Trans. Design Autom. Electr. Syst. 6(4): 471-489 (2001) |
| 42 | EE | Kamran Zarrineh,
Shambhu J. Upadhyaya,
Sreejit Chakravarty:
Automatic generation and compaction of March tests for memory arrays.
IEEE Trans. VLSI Syst. 9(6): 845-857 (2001) |
| 2000 |
|---|
| 41 | EE | Sujit T. Zachariah,
Sreejit Chakravarty,
Carl D. Roth:
A novel algorithm to extract two-node bridges.
DAC 2000: 790-793 |
| 40 | | Seonki Kim,
Sreejit Chakravarty,
Bapiraju Vinnakota:
An analysis of the delay defect detection capability of the ECR test method.
ITC 2000: 1060-1069 |
| 39 | | Sujit T. Zachariah,
Sreejit Chakravarty:
A scalable and efficient methodology to extract two node bridges from large industrial circuits.
ITC 2000: 750-759 |
| 38 | EE | Sreejit Chakravarty,
Sujit T. Zachariah:
STBM: a fast algorithm to simulate IDDQ tests forleakage faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 568-576 (2000) |
| 1999 |
|---|
| 37 | EE | Sreenivas Mandava,
Sreejit Chakravarty,
Sandip Kundu:
On Detecting Bridges Causing Timing Failures.
ICCD 1999: 400-406 |
| 36 | | Sujit T. Zachariah,
Sreejit Chakravarty:
A Comparative Study of Pseudo Stuck-At and Leakage Fault Model.
VLSI Design 1999: 91-94 |
| 35 | EE | Sreejit Chakravarty,
Vinodh Gopal:
Techniques to Encode and Compress Fault Dictionaries.
VTS 1999: 195-200 |
| 1998 |
|---|
| 34 | EE | Kamran Zarrineh,
Shambhu J. Upadhyaya,
Sreejit Chakravarty:
A new framework for generating optimal March tests for memory arrays.
ITC 1998: 73- |
| 33 | EE | Vinay Dabholkar,
Sreejit Chakravarty:
Computing Stress Tests for Gate Oxide Shorts.
VLSI Design 1998: 378-391 |
| 32 | EE | Vinay Dabholkar,
Sreejit Chakravarty,
Irith Pomeranz,
Sudhakar M. Reddy:
Techniques for minimizing power dissipation in scan and combinational circuits during test application.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1325-1333 (1998) |
| 31 | EE | Yiming Gong,
Sreejit Chakravarty:
Locating bridging faults using dynamically computed stuck-at fault dictionaries.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 876-887 (1998) |
| 1997 |
|---|
| 30 | EE | Vinay Dabholkar,
Sreejit Chakravarty:
Computing stress tests for interconnect defects.
Asian Test Symposium 1997: 143-148 |
| 29 | EE | Sreejit Chakravarty:
On the capability of delay tests to detect bridges and opens.
Asian Test Symposium 1997: 314-319 |
| 28 | EE | Yiming Gong,
Sreejit Chakravarty:
Using fault sampling to compute I/sub DDQ/ diagnostic test set.
VTS 1997: 74-79 |
| 27 | EE | Paul J. Thadikaran,
Sreejit Chakravarty,
Janak H. Patel:
Algorithms to compute bridging fault coverage of IDDQ test sets.
ACM Trans. Design Autom. Electr. Syst. 2(3): 281-305 (1997) |
| 1996 |
|---|
| 26 | EE | Paul J. Thadikaran,
Sreejit Chakravarty:
Fast Algorithms for Computer IDDQ Tests for Combination Circuits.
VLSI Design 1996: 103-106 |
| 25 | EE | Sreejit Chakravarty:
A sampling technique for diagnostic fault simulation.
VTS 1996: 192-197 |
| 24 | | Sreejit Chakravarty,
Paul J. Thadikaran:
Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits.
IEEE Trans. Computers 45(10): 1131-1140 (1996) |
| 23 | | Sreejit Chakravarty:
A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits.
IEEE Trans. Computers 45(8): 985-991 (1996) |
| 1995 |
|---|
| 22 | EE | Srikanth Venkataraman,
Ismed Hartanto,
W. Kent Fuchs,
Elizabeth M. Rudnick,
Sreejit Chakravarty,
Janak H. Patel:
Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists.
DAC 1995: 133-138 |
| 21 | | Paul J. Thadikaran,
Sreejit Chakravarty,
Janak H. Patel:
Fault Simulation ofIDDQ Tests for Bridging Faults in Sequential Circuits.
FTCS 1995: 340-349 |
| 20 | EE | Yiming Gong,
Sreejit Chakravarty:
On adaptive diagnostic test generation.
ICCAD 1995: 181-184 |
| 19 | EE | Sreejit Chakravarty,
Yiming Gong:
Voting model based diagnosis of bridging faults in combinational circuits.
VLSI Design 1995: 338-342 |
| 18 | EE | Vinay Dabholkar,
Sreejit Chakravarty,
J. Najm,
Janak H. Patel:
Cyclic stress tests for full scan circuits.
VTS 1995: 89-94 |
| 17 | | Sreejit Chakravarty,
Ramalingam Sridhar,
Shambhu J. Upadhyaya,
Yervant Zorian,
Gil Philips,
Bozena Kaminska,
Bernard Courtois:
Conference Reports.
IEEE Design & Test of Computers 12(4): 95-97 (1995) |
| 1994 |
|---|
| 16 | | Sreejit Chakravarty,
Paul J. Thadikaran:
A Study of IDDQ Subset Selection Algorithms for Bridging Faults.
ITC 1994: 403-412 |
| 15 | | Sreejit Chakravarty,
Sivaprakasam Suresh:
IDDQ Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits.
VLSI Design 1994: 179-182 |
| 1993 |
|---|
| 14 | EE | Sreejit Chakravarty,
Yiming Gong:
An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits.
DAC 1993: 520-524 |
| 13 | | Sreejit Chakravarty:
A Characterization of Binary Decision Diagrams.
IEEE Trans. Computers 42(2): 129-137 (1993) |
| 1992 |
|---|
| 12 | EE | Sreejit Chakravarty,
Minshen Liu:
Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults.
DAC 1992: 353-356 |
| 1991 |
|---|
| 11 | EE | Sreejit Chakravarty,
Xin He,
S. S. Ravi:
Minimum area layout of series-parallel transistor networks is NP-hard.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 943-949 (1991) |
| 1990 |
|---|
| 10 | EE | Sreejit Chakravarty:
On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract).
DAC 1990: 736-739 |
| 9 | | Ajay Shekhawat,
Sreejit Chakravarty:
Heuristics for the MSC Problem for Serial and Shared-Memory Computers.
ICPP (3) 1990: 64-67 |
| 8 | | Sreejit Chakravarty,
Harry B. Hunt III:
On Computing Signal Probability and Detection Probability of Stuck-at Faults.
IEEE Trans. Computers 39(11): 1369-1377 (1990) |
| 7 | EE | Sreejit Chakravarty,
S. S. Ravi:
Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(3): 329-331 (1990) |
| 1989 |
|---|
| 6 | | Sreejit Chakravarty:
A Testable Realization of CMOS Combinational Circuits.
ITC 1989: 509-518 |
| 5 | | Sreejit Chakravarty,
Harry B. Hunt III:
A Note on Detecting Sneak Paths in Transistor Networks.
IEEE Trans. Computers 38(6): 861-864 (1989) |
| 4 | | Sreejit Chakravarty,
Harry B. Hunt III,
S. S. Ravi,
Daniel J. Rosenkrantz:
The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits.
IEEE Trans. Computers 38(6): 865-869 (1989) |
| 3 | EE | Sreejit Chakravarty:
On the complexity of computing tests for CMOS gates.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(9): 973-980 (1989) |
| 1988 |
|---|
| 2 | | Sreejit Chakravarty,
Shambhu J. Upadhyaya:
A Unified Approach to Designing Fault-Tolerant Processor Ensembles.
ICPP (1) 1988: 339-342 |
| 1986 |
|---|
| 1 | | Sreejit Chakravarty,
Harry B. Hunt III:
On the Computation of Detection Probability for Multiple Faults.
ITC 1986: 252-262 |
