| |
| 2008 | ||
|---|---|---|
| 4 | EE | Dong Xiang, Mingjing Chen, Jia-Guang Sun: Scan BIST with biased scan test signals. Science in China Series F: Information Sciences 51(7): 881-895 (2008) |
| 2007 | ||
| 3 | EE | Mingjing Chen, Alex Orailoglu: Circuit-level mismatch modelling and yield optimization for CMOS analog circuits. ICCD 2007: 526-532 |
| 2 | EE | Dong Xiang, Mingjing Chen, Hideo Fujiwara: Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. IEEE Trans. Computers 56(12): 1619-1628 (2007) |
| 2006 | ||
| 1 | EE | Mingjing Chen, Hosam Haggag, Alex Orailoglu: Decision Tree Based Mismatch Diagnosis in Analog Circuits. VTS 2006: 278-285 |
| 1 | Hideo Fujiwara | [2] |
| 2 | Hosam Haggag | [1] |
| 3 | Alex Orailoglu | [1] [3] |
| 4 | Jia-Guang Sun (Jiaguang Sun) | [4] |
| 5 | Dong Xiang | [2] [4] |