Sangyeun Cho

2007
17		Lynn Choi, Yunheung Paek, Sangyeun Cho: Advances in Computer Systems Architecture, 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings Springer 2007
16	EE	Sangyeun Cho: I-cache multi-banking and vertical interleaving. ACM Great Lakes Symposium on VLSI 2007: 14-19
15	EE	Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem: CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications. ISPASS 2007: 230-241
14	EE	Choongyeun Cho, Daeik Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, Robert Trzcinski: A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology. ISQED 2007: 699-702
13	EE	Hyunjin Lee, Sangyeun Cho, Bruce R. Childers: Performance of Graceful Degradation for Cache Faults. ISVLSI 2007: 409-415
12	EE	Sangyeun Cho, Lei Jin, Kiyeon Lee: Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems. RTCSA 2007: 3-11
2006
11	EE	Lei Jin, Sangyeun Cho: Reducing cache traffic and energy with macro data load. ISLPED 2006: 147-150
10	EE	Sangyeun Cho, Lei Jin: Managing Distributed, Shared L2 Caches through OS-Level Page Allocation. MICRO 2006: 455-468
9	EE	Lei Jin, Hyunjin Lee, Sangyeun Cho: A flexible data to L2 cache mapping approach for future multicore processors. Memory System Performance and Correctness 2006: 92-101
2001
8		Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woong Jeong: A Low-Power Cache Design for CalmRISCTM-Based Systems. ICCD 2001: 394-399
7	EE	Sangyeun Cho, Pen-Chung Yew, Gyungho Lee: A High-Bandwidth Memory Pipeline for Wide Issue Processors. IEEE Trans. Computers 50(7): 709-723 (2001)
1999
6	EE	Sangyeun Cho, Pen-Chung Yew, Gyungho Lee: Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor. ISCA 1999: 100-110
5	EE	Sangyeun Cho, Pen-Chung Yew, Gyungho Lee: Access Region Locality for High-Bandwidth Processor Memory System Design. MICRO 1999: 136-146
4		Sangyeun Cho, Jinseok Kong, Gyungho Lee: Coherence and Replacement Protocol of DICE-A Bus-Based COMA Multiprocessor. J. Parallel Distrib. Comput. 57(1): 14-32 (1999)
1998
3	EE	Sangyeun Cho, Jenn-Yuan Tsai, Yonghong Song, Bixia Zheng, Stephen J. Schwinn, Xin Wang, Qing Zhao, Zhiyuan Li, David J. Lilja, Pen-Chung Yew: High-Level Information - An Approach for Integrating Front-End and Back-End Compilers. ICPP 1998: 346-355
1996
2		Sangyeun Cho, Gyungho Lee: Reducing Coherence Overhead in Shared-Bus Multiprocessors. Euro-Par, Vol. II 1996: 492-497
1	EE	Gyungho Lee, Bland Quattlebaum, Sangyeun Cho, Larry L. Kinney: Global Bus Design of a Bus-Based COMA Multiprocessor DICE. ICCD 1996: 231-

Coauthor Index

1	Bruce R. Childers	[13]
2	Choongyeun Cho	[14]
3	Lynn Choi	[17]
4	Mohammad H. Hammoud	[15]
5	Seh-Woong Jeong	[8]
6	Lei Jin	[9] [10] [11] [12]
7	Wooyoung Jung	[8]
8	Daeik Kim	[14]
9	Jonghae Kim	[14]
10	Yongchun Kim	[8]
11	Larry L. Kinney	[1]
12	Jinseok Kong	[4]
13	Gyungho Lee	[1] [2] [4] [5] [6] [7]
14	Hyunjin Lee	[9] [13]
15	Kiyeon Lee	[12]
16	Zhiyuan Li	[3]
17	David J. Lilja	[3]
18	Daihyun Lim	[14]
19	Joel R. Martin	[15]
20	Rami G. Melhem	[15]
21	Yunheung Paek	[17]
22	Jean-Olivier Plouchart	[14]
23	Bland Quattlebaum	[1]
24	Stephen J. Schwinn	[3]
25	Yonghong Song	[3]
26	Robert Trzcinski	[14]
27	Jenn-Yuan Tsai	[3]
28	Xin Wang	[3]
29	Ruibin Xu	[15]
30	Pen-Chung Yew	[3] [5] [6] [7]
31	Qing Zhao	[3]
32	Bixia Zheng	[3]

Colors in the list of coauthors