| 2008 |
|---|
| 149 | EE | Luis F. G. Sarmenta,
Marten van Dijk,
Jonathan Rhodes,
Srinivas Devadas:
Offline count-limited certificates.
SAC 2008: 2145-2152 |
| 2007 |
|---|
| 148 | EE | G. Edward Suh,
Srinivas Devadas:
Physical Unclonable Functions for Device Authentication and Secret Key Generation.
DAC 2007: 9-14 |
| 147 | EE | G. Edward Suh,
Charles W. O'Donnell,
Srinivas Devadas:
Aegis: A Single-Chip Secure Processor.
IEEE Design & Test of Computers 24(6): 570-580 (2007) |
| 2006 |
|---|
| 146 | EE | Blaise Gassend,
Charles W. O'Donnell,
William Thies,
Andrew Lee,
Marten van Dijk,
Srinivas Devadas:
Predicting Secondary Structure of All-Helical Proteins Using Hidden Markov Support Vector Machines.
PRIB 2006: 93-104 |
| 145 | EE | Marten van Dijk,
Emina Torlak,
Blaise Gassend,
Srinivas Devadas:
A Generalized Two-Phase Analysis of Knowledge Flows in Security Protocols
CoRR abs/cs/0605097: (2006) |
| 144 | EE | Emina Torlak,
Marten van Dijk,
Blaise Gassend,
Daniel Jackson,
Srinivas Devadas:
Knowledge Flow Analysis for Security Protocols
CoRR abs/cs/0605109: (2006) |
| 143 | EE | Marten van Dijk,
Dwaine E. Clarke,
Blaise Gassend,
G. Edward Suh,
Srinivas Devadas:
Speeding up Exponentiation using an Untrusted Computational Resource.
Des. Codes Cryptography 39(2): 253-273 (2006) |
| 2005 |
|---|
| 142 | EE | Dwaine E. Clarke,
G. Edward Suh,
Blaise Gassend,
Ajay Sudan,
Marten van Dijk,
Srinivas Devadas:
Towards Constant Bandwidth Overhead Integrity Checking of Untrusted Data.
IEEE Symposium on Security and Privacy 2005: 139-153 |
| 141 | EE | G. Edward Suh,
Charles W. O'Donnell,
Ishan Sachdev,
Srinivas Devadas:
Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions.
ISCA 2005: 25-36 |
| 140 | EE | Daihyun Lim,
Jae W. Lee,
Blaise Gassend,
G. Edward Suh,
Marten van Dijk,
Srinivas Devadas:
Extracting secret keys from integrated circuits.
IEEE Trans. VLSI Syst. 13(10): 1200-1205 (2005) |
| 2004 |
|---|
| 139 | EE | G. Edward Suh,
Jae W. Lee,
David Zhang,
Srinivas Devadas:
Secure program execution via dynamic information flow tracking.
ASPLOS 2004: 85-96 |
| 138 | EE | Hari Balakrishnan,
Srinivas Devadas,
Douglas Ehlert,
Arvind:
Rate Guarantees and Overload Protection in Input-Queued Switches.
INFOCOM 2004 |
| 137 | EE | Blaise Gassend,
Daihyun Lim,
Dwaine E. Clarke,
Marten van Dijk,
Srinivas Devadas:
Identification and authentication of integrated circuits.
Concurrency - Practice and Experience 16(11): 1077-1098 (2004) |
| 136 | EE | Sanjay Raman,
Dwaine E. Clarke,
Matt Burnside,
Srinivas Devadas,
Ronald L. Rivest:
Access-controlled resource discovery in pervasive networks.
Concurrency - Practice and Experience 16(11): 1099-1120 (2004) |
| 135 | EE | G. Edward Suh,
Larry Rudolph,
Srinivas Devadas:
Dynamic Partitioning of Shared Cache Memory.
The Journal of Supercomputing 28(1): 7-26 (2004) |
| 2003 |
|---|
| 134 | EE | Dwaine E. Clarke,
Srinivas Devadas,
Marten van Dijk,
Blaise Gassend,
G. Edward Suh:
Incremental Multiset Hash Functions and Their Application to Memory Integrity Checking.
ASIACRYPT 2003: 188-207 |
| 133 | EE | Prabhat Jain,
G. Edward Suh,
Srinivas Devadas:
Embedded intelligent SRAM.
DAC 2003: 869-874 |
| 132 | EE | Blaise Gassend,
G. Edward Suh,
Dwaine E. Clarke,
Marten van Dijk,
Srinivas Devadas:
Caches and Hash Trees for Efficient Memory Integrity.
HPCA 2003: 295-306 |
| 131 | EE | G. Edward Suh,
Dwaine E. Clarke,
Blaise Gassend,
Marten van Dijk,
Srinivas Devadas:
AEGIS: architecture for tamper-evident and tamper-resistant processing.
ICS 2003: 160-171 |
| 130 | EE | G. Edward Suh,
Dwaine E. Clarke,
Blaise Gassend,
Marten van Dijk,
Srinivas Devadas:
Efficient Memory Integrity Verification and Encryption for Secure Processors.
MICRO 2003: 339-350 |
| 129 | | Blaise Gassend,
Dwaine E. Clarke,
Marten van Dijk,
Srinivas Devadas:
Delay-Based Circuit Authentication and Applications.
SAC 2003: 294-301 |
| 128 | | Sanjay Raman,
Dwaine E. Clarke,
Matt Burnside,
Srinivas Devadas,
Ronald L. Rivest:
Access-Controlled Resource Discovery for Pervasive Networks.
SAC 2003: 338-345 |
| 127 | EE | George Hadjiyiannis,
Srinivas Devadas:
Techniques for accurate performance evaluation in architecture exploration.
IEEE Trans. VLSI Syst. 11(4): 601-615 (2003) |
| 2002 |
|---|
| 126 | EE | Blaise Gassend,
Dwaine E. Clarke,
Marten van Dijk,
Srinivas Devadas:
Silicon physical random functions.
ACM Conference on Computer and Communications Security 2002: 148-160 |
| 125 | EE | Blaise Gassend,
Dwaine E. Clarke,
Marten van Dijk,
Srinivas Devadas:
Controlled Physical Random Functions.
ACSAC 2002: 149-160 |
| 124 | EE | G. Edward Suh,
Srinivas Devadas,
Larry Rudolph:
A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning.
HPCA 2002: 117- |
| 123 | EE | Dwaine E. Clarke,
Blaise Gassend,
Thomas Kotwal,
Matt Burnside,
Marten van Dijk,
Srinivas Devadas,
Ronald L. Rivest:
The Untrusted Computer Problem and Camera-Based Authentication.
Pervasive 2002: 114-124 |
| 122 | EE | Matt Burnside,
Dwaine E. Clarke,
Todd Mills,
Andrew Maywah,
Srinivas Devadas,
Ronald L. Rivest:
Proxy-based security protocols in networked mobile devices.
SAC 2002: 265-272 |
| 121 | EE | Farzan Fallah,
Pranav Ashar,
Srinivas Devadas:
Functional vector generation for sequential HDL models under an observability-based code coverage metric.
IEEE Trans. VLSI Syst. 10(6): 919-923 (2002) |
| 2001 |
|---|
| 120 | EE | Prabhat Jain,
Srinivas Devadas,
Daniel W. Engels,
Larry Rudolph:
Software-Assisted Cache Replacement Mechanisms for Embedded Systems.
ICCAD 2001: 119-126 |
| 119 | EE | G. Edward Suh,
Srinivas Devadas,
Larry Rudolph:
Analytical cache models with applications to cache partitioning.
ICS 2001: 1-12 |
| 118 | EE | G. Edward Suh,
Larry Rudolph,
Srinivas Devadas:
Effects of Memory Performance on Parallel Job Scheduling.
JSSPP 2001: 116-132 |
| 117 | EE | Farzan Fallah,
Srinivas Devadas,
Kurt Keutzer:
OCCOM-efficient computation of observability-based code coveragemetrics for functional verification.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(8): 1003-1015 (2001) |
| 116 | EE | Farzan Fallah,
Srinivas Devadas,
Kurt Keutzer:
Functional vector generation for HDL models using linearprogramming and Boolean satisfiability.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(8): 994-1002 (2001) |
| 2000 |
|---|
| 115 | | L. Miguel Silveira,
Srinivas Devadas,
Ricardo Augusto da Luz Reis:
VLSI: Systems on a Chip, IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI '99), December 1-4, 1999, Lisbon, Portugal
Kluwer 2000 |
| 114 | EE | Derek Chiou,
Prabhat Jain,
Larry Rudolph,
Srinivas Devadas:
Application-specific memory management for embedded systems using software-controlled caches.
DAC 2000: 416-419 |
| 113 | | José C. Costa,
Srinivas Devadas,
José Monteiro:
Observability Analysis of Embedded Software for Coverage-Directed Validation.
ICCAD 2000: 27-32 |
| 112 | EE | Farzan Fallah,
Stan Y. Liao,
Srinivas Devadas:
Solving covering problems using LPR-based lower bounds.
IEEE Trans. VLSI Syst. 8(1): 9-17 (2000) |
| 1999 |
|---|
| 111 | EE | Farzan Fallah,
Pranav Ashar,
Srinivas Devadas:
Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage.
DAC 1999: 666-671 |
| 110 | EE | George Hadjiyiannis,
Pietro Russo,
Srinivas Devadas:
A Methodology for Accurate Performance Evaluation in Architecture Exploration.
DAC 1999: 927-932 |
| 109 | | Srinivas Devadas,
Sharad Malik,
José C. Monteiro,
Luciano Lavagno:
CAD Techniques for Embedded System Design.
VLSI Design 1999: 608 |
| 108 | EE | Stan Y. Liao,
Srinivas Devadas,
Kurt Keutzer:
A text-compression-based method for code size minimization in embedded systems.
ACM Trans. Design Autom. Electr. Syst. 4(1): 12-38 (1999) |
| 1998 |
|---|
| 107 | EE | Farzan Fallah,
Srinivas Devadas,
Kurt Keutzer:
OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification.
DAC 1998: 152-157 |
| 106 | EE | Silvina Hanono,
Srinivas Devadas:
Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator.
DAC 1998: 510-515 |
| 105 | EE | Farzan Fallah,
Srinivas Devadas,
Kurt Keutzer:
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability.
DAC 1998: 528-533 |
| 104 | EE | Srinivas Devadas,
Kurt Keutzer:
An algorithmic approach to optimizing fault coverage for BIST logic synthesis.
ITC 1998: 164- |
| 103 | EE | Stan Y. Liao,
Kurt Keutzer,
Steven W. K. Tjiang,
Srinivas Devadas:
A new viewpoint on code generation for directed acyclic graphs.
ACM Trans. Design Autom. Electr. Syst. 3(1): 51-75 (1998) |
| 102 | EE | José C. Monteiro,
Srinivas Devadas,
Abhijit Ghosh:
Sequential logic optimization for low power using input-disabling precomputation architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 279-284 (1998) |
| 101 | EE | Stan Y. Liao,
Srinivas Devadas,
Kurt Keutzer:
Code density optimization for embedded DSP processors using data compression techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(7): 601-608 (1998) |
| 100 | EE | Kenneth Y. Yun,
Bill Lin,
David L. Dill,
Srinivas Devadas:
BDD-based synthesis of extended burst-mode controllers.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 782-792 (1998) |
| 99 | EE | George Hadjiyiannis,
Anantha Chandrakasan,
Srinivas Devadas:
A low power, low bandwidth protocol for remote wireless terminals.
Wireless Networks 4(1): 3-15 (1998) |
| 1997 |
|---|
| 98 | EE | Stan Y. Liao,
Srinivas Devadas:
Solving Covering Problems Using LPR-Based Lower Bounds.
DAC 1997: 117-120 |
| 97 | EE | Ashok Sudarsanam,
Stan Y. Liao,
Srinivas Devadas:
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures.
DAC 1997: 287-292 |
| 96 | EE | George Hadjiyiannis,
Silvina Hanono,
Srinivas Devadas:
ISDL: An Instruction Set Description Language for Retargetability.
DAC 1997: 299-302 |
| 95 | EE | José C. Costa,
José C. Monteiro,
Srinivas Devadas:
Switching activity estimation using limited depth reconvergent path analysis.
ISLPED 1997: 184-189 |
| 94 | EE | José C. Monteiro,
Srinivas Devadas,
Abhijit Ghosh,
Kurt Keutzer,
Jacob K. White:
Estimation of average switching activity in combinational logic circuits using symbolic simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 121-127 (1997) |
| 1996 |
|---|
| 93 | EE | José Monteiro,
Srinivas Devadas,
Pranav Ashar,
Ashutosh Mauskar:
Scheduling Techniques to Enable Power Management.
DAC 1996: 349-352 |
| 92 | EE | Srinivas Devadas,
Abhijit Ghosh,
Kurt Keutzer:
An observability-based code coverage metric for functional simulation.
ICCAD 1996: 418-425 |
| 91 | EE | Stan Y. Liao,
Srinivas Devadas,
Kurt Keutzer,
Steven W. K. Tjiang,
Albert Wang:
Storage Assignment to Decrease Code Size.
ACM Trans. Program. Lang. Syst. 18(3): 235-253 (1996) |
| 90 | EE | Chi-Ying Tsui,
José C. Monteiro,
Massoud Pedram,
Srinivas Devadas,
Alvin M. Despain,
Bill Lin:
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence].
IEEE Trans. VLSI Syst. 4(4): 495 (1996) |
| 89 | EE | Srinivas Devadas,
Kurt Keutzer:
Addendum to "Synthesis of robust delay-fault testable circuits: Theory".
IEEE Trans. on CAD of Integrated Circuits and Systems 15(4): 445-446 (1996) |
| 1995 |
|---|
| 88 | EE | Stan Y. Liao,
Srinivas Devadas,
Kurt Keutzer:
Code density optimization for embedded DSP processors using data compression techniques.
ARVLSI 1995: 272-285 |
| 87 | EE | José Monteiro,
John Rinderknecht,
Srinivas Devadas,
Abhijit Ghosh:
Optimization of combinational and sequential logic circuits for low power using precomputation.
ARVLSI 1995: 430-444 |
| 86 | EE | Srinivas Devadas,
Sharad Malik:
A Survey of Optimization Techniques Targeting Low Power VLSI Circuits.
DAC 1995: 242-247 |
| 85 | EE | Stan Y. Liao,
Srinivas Devadas,
Kurt Keutzer,
Steven W. K. Tjiang,
Albert Wang:
Code Optimization Techniques for Embedded DSP Microprocessors.
DAC 1995: 599-604 |
| 84 | EE | Stan Y. Liao,
Srinivas Devadas,
Kurt Keutzer,
Steven W. K. Tjiang:
Instruction selection using binate covering for code size optimization.
ICCAD 1995: 393-399 |
| 83 | EE | José Monteiro,
Srinivas Devadas:
Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs.
ISLPD 1995: 33-38 |
| 82 | | Stan Y. Liao,
Srinivas Devadas,
Kurt Keutzer,
Steven W. K. Tjiang,
Albert Wang:
Storage Assignment to Decrease Code Size.
PLDI 1995: 186-195 |
| 81 | EE | Chi-Ying Tsui,
José C. Monteiro,
Massoud Pedram,
Srinivas Devadas,
Alvin M. Despain,
Bill Lin:
Power estimation methods for sequential logic circuits.
IEEE Trans. VLSI Syst. 3(3): 404-416 (1995) |
| 80 | EE | Amelia Shen,
Srinivas Devadas,
Abhijit Ghosh:
Probabilistic manipulation of Boolean functions using free Boolean diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 87-95 (1995) |
| 79 | EE | Bill Lin,
Srinivas Devadas:
Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 974-985 (1995) |
| 1994 |
|---|
| 78 | | Guido Araujo,
Srinivas Devadas,
Kurt Keutzer,
Stan Y. Liao,
Sharad Malik,
Ashok Sudarsanam,
Steven W. K. Tjiang,
Albert Wang:
Challenges in code generation for embedded processors.
Code Generation for Embedded Processors 1994: 48-64 |
| 77 | EE | José C. Monteiro,
Srinivas Devadas,
Bill Lin:
A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits.
DAC 1994: 12-17 |
| 76 | EE | Vishal Bhagwati,
Srinivas Devadas:
Automatic Verification of Pipelined Microprocessors.
DAC 1994: 603-608 |
| 75 | EE | Bill Lin,
Srinivas Devadas:
Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams.
ICCAD 1994: 542-549 |
| 74 | EE | Kenneth Y. Yun,
Bill Lin,
David L. Dill,
Srinivas Devadas:
Performance-driven synthesis of asynchronous controllers.
ICCAD 1994: 550-557 |
| 73 | EE | Mazhar Alidina,
José C. Monteiro,
Srinivas Devadas,
Abhijit Ghosh,
Marios C. Papaefthymiou:
Precomputation-based sequential logic optimization for low power.
ICCAD 1994: 74-81 |
| 72 | | José C. Monteiro,
James H. Kukula,
Srinivas Devadas,
Horácio C. Neto:
Bitwise Encoding of Finite State Machines.
VLSI Design 1994: 379-382 |
| 71 | EE | Srinivas Devadas,
Kurt Keutzer,
Sharad Malik,
Albert Wang:
Certified timing verification and the transition delay of a logic circuit.
IEEE Trans. VLSI Syst. 2(3): 333-342 (1994) |
| 70 | EE | Mazhar Alidina,
José C. Monteiro,
Srinivas Devadas,
Abhijit Ghosh,
Marios C. Papaefthymiou:
Precomputation-based sequential logic optimization for low power.
IEEE Trans. VLSI Syst. 2(4): 426-436 (1994) |
| 69 | EE | Filip Van Aelten,
Jonathan Allen,
Srinivas Devadas:
Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 122-134 (1994) |
| 68 | EE | Srinivas Devadas,
Kurt Keutzer,
Sharad Malik,
Albert Wang:
Event suppression: improving the efficiency of timing simulation for synchronous digital circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 814-822 (1994) |
| 1993 |
|---|
| 67 | EE | José C. Monteiro,
Srinivas Devadas,
Abhijit Ghosh:
Retiming sequential circuits for low power.
ICCAD 1993: 398-402 |
| 66 | EE | Amelia Shen,
Srinivas Devadas,
Abhijit Ghosh:
Probabilistic construction and manipulation of free Boolean diagrams.
ICCAD 1993: 544-583 |
| 65 | EE | Stan Y. Liao,
Srinivas Devadas,
Abhijit Ghosh:
Boolean factorization using multiple-valued minimization.
ICCAD 1993: 606-611 |
| 64 | | Pranav Ashar,
Srinivas Devadas,
Kurt Keutzer:
Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks.
Formal Methods in System Design 2(1): 93-112 (1993) |
| 63 | EE | Horng-Fei Jyu,
Sharad Malik,
Srinivas Devadas,
K. W. Keutzer:
Statistical timing analysis of combinational logic circuits.
IEEE Trans. VLSI Syst. 1(2): 126-137 (1993) |
| 62 | EE | Srinivas Devadas,
Kurt Keutzer,
Sharad Malik:
Computation of floating mode delay in combinational circuits: theory and algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1913-1923 (1993) |
| 61 | EE | Srinivas Devadas,
Kurt Keutzer,
Sharad Malik,
Albert Wang:
Computation of floating mode delay in combinational circuits: practice and implementation.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1924-1936 (1993) |
| 60 | EE | Filip Van Aelten,
Jonathan Allen,
Srinivas Devadas:
Verification of relations between synchronous machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1947-1959 (1993) |
| 59 | EE | Abhijit Ghosh,
Srinivas Devadas,
A. Richard Newton:
Sequential test generation and synthesis for testability at the register-transfer and logic levels.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 579-598 (1993) |
| 58 | EE | Srinivas Devadas:
Comparing two-level and ordered binary decision diagram representations of logic functions.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 722-723 (1993) |
| 57 | EE | Kwang-Ting Cheng,
Srinivas Devadas,
Kurt Keutzer:
Delay-fault test generation and synthesis for testability under a standard scan design methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1217-1231 (1993) |
| 1992 |
|---|
| 56 | EE | Abhijit Ghosh,
Srinivas Devadas,
Kurt Keutzer,
Jacob White:
Estimation of Average Switching Activity in Combinational and Sequential Circuits.
DAC 1992: 253-259 |
| 55 | EE | Srinivas Devadas,
Kurt Keutzer,
Sharad Malik,
Albert Wang:
Certified Timing Verification and the Transition Delay of a Logic Circuit.
DAC 1992: 549-555 |
| 54 | EE | Filip Van Aelten,
Stan Y. Liao,
Jonathan Allen,
Srinivas Devadas:
Automatic generation and verification of sufficient correctness properties for synchronous processors.
ICCAD 1992: 183-187 |
| 53 | EE | Srinivas Devadas,
Kurt Keutzer,
Sharad Malik,
Albert Wang:
Verification of asynchronous interface circuits with bounded wire delays.
ICCAD 1992: 188-195 |
| 52 | EE | Amelia Shen,
Abhijit Ghosh,
Srinivas Devadas,
Kurt Keutzer:
On average power dissipation and random pattern testability of CMOS combinational logic networks.
ICCAD 1992: 402-407 |
| 51 | | Srinivas Devadas,
Horng-Fei Jyu,
Kurt Keutzer,
Sharad Malik:
Statistical Timing Analysis of Combinational Circuits.
ICCD 1992: 38-43 |
| 50 | EE | Srinivas Devadas,
Kurt Keutzer:
Synthesis of robust delay-fault-testable circuits: theory.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 87-101 (1992) |
| 49 | EE | Srinivas Devadas,
Kurt Keutzer:
Validatable nonrobust delay-fault testable circuits via logic synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(12): 1559-1573 (1992) |
| 48 | EE | Srinivas Devadas,
Kurt Keutzer:
Synthesis of robust delay-fault-testable circuits: practice.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(3): 277-300 (1992) |
| 47 | EE | Srinivas Devadas,
Kurt Keutzer,
Jacob K. White:
Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(3): 373-383 (1992) |
| 46 | EE | Michael J. Bryan,
Srinivas Devadas,
Kurt Keutzer:
Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 800-803 (1992) |
| 45 | EE | Abhijit Ghosh,
Srinivas Devadas,
A. Richard Newton:
Heuristic minimization of Boolean relations using testing techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1166-1172 (1992) |
| 1991 |
|---|
| 44 | EE | Srinivas Devadas,
Kurt Keutzer,
Sharad Malik:
A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults.
DAC 1991: 359-365 |
| 43 | EE | Kwang-Ting Cheng,
Srinivas Devadas,
Kurt Keutzer:
Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology.
DAC 1991: 80-86 |
| 42 | | Srinivas Devadas,
Kurt Keutzer,
Sharad Malik:
Delay Computation in Combinational Logic Circuits: Theory and Algorithms.
ICCAD 1991: 176-179 |
| 41 | | Filip Van Aelten,
Jonathan Allen,
Srinivas Devadas:
Verification of Relations Between Synchronous Machines.
ICCAD 1991: 380-383 |
| 40 | | James H. Kukula,
Srinivas Devadas:
Finite State Machine Decomposition by Transition Pairing.
ICCAD 1991: 414-417 |
| 39 | | Srinivas Devadas,
Kurt Keutzer,
A. S. Krishnakumar:
Design Verfication and Reachability Analysis Using Algebraic Manipulation.
ICCD 1991: 250-258 |
| 38 | | Pranav Ashar,
Abhijit Ghosh,
Srinivas Devadas:
Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams.
ICCD 1991: 259-264 |
| 37 | | Kwang-Ting Cheng,
Srinivas Devadas,
Kurt Keutzer:
A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits.
ITC 1991: 403-410 |
| 36 | | Pranav Ashar,
Srinivas Devadas,
Kurt Keutzer:
Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks.
ITC 1991: 887-896 |
| 35 | EE | Srinivas Devadas,
A. Richard Newton:
Exact algorithms for output encoding, state assignment, and four-level Boolean minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 13-27 (1991) |
| 34 | EE | Srinivas Devadas,
Kurt Keutzer:
A unified approach to the synthesis of fully testable sequential machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 39-50 (1991) |
| 33 | EE | Srinivas Devadas:
Optimizing interacting finite state machines using sequential don't cares.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(12): 1473-1484 (1991) |
| 32 | EE | Pranav Ashar,
Srinivas Devadas,
A. Richard Newton:
Optimum and heuristic algorithms for an approach to finite state machine decomposition.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(3): 296-310 (1991) |
| 31 | EE | Pranav Ashar,
Srinivas Devadas,
A. Richard Newton:
Irredundant interacting sequential machines via optimal logic synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(3): 311-325 (1991) |
| 30 | EE | Abhijit Ghosh,
Srinivas Devadas,
A. Richard Newton:
Test generation and verification for highly sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 652-667 (1991) |
| 1990 |
|---|
| 29 | EE | Abhijit Ghosh,
Srinivas Devadas,
A. Richard Newton:
Verification of Interacting Sequential Circuits.
DAC 1990: 213-219 |
| 28 | EE | Srinivas Devadas,
Kurt Keutzer:
Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits.
DAC 1990: 221-227 |
| 27 | EE | Abhijit Ghosh,
Srinivas Devadas,
A. Richard Newton:
Sequential Test Generation at the Register-Transfer and Logic Levels.
DAC 1990: 580-586 |
| 26 | EE | Pranav Ashar,
Srinivas Devadas,
A. Richard Newton:
A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines.
DAC 1990: 601-606 |
| 25 | | Srinivas Devadas,
Kurt Keutzer:
An Automata-Theoretic Approach to Behavioral Equivalence.
ICCAD 1990: 30-33 |
| 24 | | Michael J. Bryan,
Srinivas Devadas,
Kurt Keutzer:
Testability-Preserving Circuit Transformations.
ICCAD 1990: 456-459 |
| 23 | | Pranav Ashar,
Abhijit Ghosh,
Srinivas Devadas,
A. Richard Newton:
Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test.
ICCAD 1990: 84-87 |
| 22 | | Srinivas Devadas:
Minimization of Functions with Multiple-Valued Outputs: Theory and Applications.
ISMVL 1990: 308-315 |
| 21 | EE | Srinivas Devadas,
Hi-Keung Tony Ma,
A. Richard Newton,
Alberto L. Sangiovanni-Vincentelli:
Irredundant sequential machines via optimal logic synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(1): 8-18 (1990) |
| 20 | EE | Srinivas Devadas,
Hi-Keung Tony Ma:
Easily testable PLA-based finite state machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(6): 604-611 (1990) |
| 1989 |
|---|
| 19 | EE | Srinivas Devadas:
Approaches to Multi-level Sequential Logic Synthesis.
DAC 1989: 270-276 |
| 18 | EE | Srinivas Devadas:
General Decomposition of Sequential Machines: Relationships to State Assignment.
DAC 1989: 314-320 |
| 17 | | Srinivas Devadas:
Delay Test Generation for Synchronous Sequential Circuits.
ITC 1989: 144-152 |
| 16 | | Srinivas Devadas,
Hi-Keung Tony Ma,
A. Richard Newton:
Redundancies and Don't Cares in Sequential Logic Synthesis.
ITC 1989: 491-500 |
| 15 | EE | Srinivas Devadas,
Hi-Keung Tony Ma,
A. Richard Newton,
Alberto L. Sangiovanni-Vincentelli:
A synthesis and optimization procedure for fully and easily testable sequential machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(10): 1100-1107 (1989) |
| 14 | EE | Srinivas Devadas,
A. Richard Newton:
Decomposition and factorization of sequential finite state machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(11): 1206-1217 (1989) |
| 13 | EE | Hi-Keung Tony Ma,
Srinivas Devadas,
Ruey-Sing Wei,
Alberto L. Sangiovanni-Vincentelli:
Logic verification algorithms and their parallel implementation.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(2): 181-189 (1989) |
| 12 | EE | Srinivas Devadas,
A. Richard Newton:
Algorithms for hardware allocation in data path synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(7): 768-781 (1989) |
| 1988 |
|---|
| 11 | | Srinivas Devadas,
Hi-Keung Tony Ma,
A. Richard Newton,
Alberto L. Sangiovanni-Vincentelli:
Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines.
ITC 1988: 621-630 |
| 10 | | Hi-Keung Tony Ma,
A. Richard Newton,
Srinivas Devadas,
Alberto L. Sangiovanni-Vincentelli:
An Incomplete Scan Design Approach to Test Generation for Sequential Machines.
ITC 1988: 730-734 |
| 9 | EE | Hi-Keung Tony Ma,
Srinivas Devadas,
A. Richard Newton,
Alberto L. Sangiovanni-Vincentelli:
Test generation for sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(10): 1081-1093 (1988) |
| 8 | EE | Srinivas Devadas,
Hi-Keung Tony Ma,
A. Richard Newton,
Alberto L. Sangiovanni-Vincentelli:
MUSTANG: state assignment of finite state machines targeting multilevel logic implementations.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(12): 1290-1300 (1988) |
| 7 | EE | Douglas Braun,
Jeffrey L. Burns,
Fabio Romeo,
Alberto L. Sangiovanni-Vincentelli,
Kartikeya Mayaram,
Srinivas Devadas,
Hi-Keung Tony Ma:
Techniques for multilayer channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(6): 698-712 (1988) |
| 6 | EE | Srinivas Devadas,
Hi-Keung Tony Ma,
A. Richard Newton:
On the verification of sequential machines at differing levels of abstraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(6): 713-722 (1988) |
| 1987 |
|---|
| 5 | EE | Srinivas Devadas,
Hi-Keung Tony Ma,
A. Richard Newton:
On the Verification of Sequential Machines at Differing Levels of Abstraction.
DAC 1987: 271-276 |
| 4 | EE | Hi-Keung Tony Ma,
Srinivas Devadas,
Alberto L. Sangiovanni-Vincentelli,
R. Wei:
Logic Verification Algorithms and Their Parallel Implementation.
DAC 1987: 283-290 |
| 3 | EE | Srinivas Devadas,
A. Richard Newton:
Topological Optimization of Multiple-Level Array Logic.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(6): 915-941 (1987) |
| 1986 |
|---|
| 2 | EE | Douglas Braun,
Jeffrey L. Burns,
Srinivas Devadas,
Hi-Keung Tony Ma,
Kartikeya Mayaram,
Fabio Romeo,
Alberto L. Sangiovanni-Vincentelli:
Chameleon: a new multi-layer channel router.
DAC 1986: 495-502 |
| 1 | EE | Srinivas Devadas,
A. Richard Newton:
GENIE: a generalized array optimizer for VLSI synthesis.
DAC 1986: 631-637 |
