Ran Ginosar

2008
46	EE	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Timing optimization in logic with interconnect. SLIP 2008: 19-26
45	EE	Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar: Parallel vs. serial on-chip communication. SLIP 2008: 43-50
2007
44	EE	Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny: High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. ASYNC 2007: 3-14
43	EE	Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Routing table minimization for irregular mesh NoCs. DATE 2007: 942-947
42	EE	Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny: The Power of Priority: NoC Based Distributed Cache Coherency. NOCS 2007: 117-126
41	EE	Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Access Regulation to Hot-Modules in Wormhole NoCs. NOCS 2007: 137-148
40	EE	Rostislav (Reuven) Dobkin, Ran Ginosar, Israel Cidon: QNoC Asynchronous Router with Dynamic Virtual Channel Allocation. NOCS 2007: 218
39	EE	Rami Rom, Jacob Erel, Michael Glikson, Randy A. Lieberman, Kobi Rosenblum, Ofer Binah, Ran Ginosar, David L. Hayes: Adaptive Cardiac Resynchronization Therapy Device Based on Spiking Neurons Architecture and Reinforcement Learning Scheme. IEEE Transactions on Neural Networks 18(2): 542-550 (2007)
2006
38	EE	Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny: Fast Asynchronous Shift Register for Bit-Serial Communication. ASYNC 2006: 117-127
37	EE	Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Efficient link capacity and QoS design for network-on-chip. DATE 2006: 9-14
36	EE	Uri Frank, Tsachy Kapschitz, Ran Ginosar: A predictive synchronizer for periodic clock domains. Formal Methods in System Design 28(2): 171-186 (2006)
35	EE	Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou: High Rate Data Synchronization in GALS SoCs. IEEE Trans. VLSI Syst. 14(10): 1063-1074 (2006)
34	EE	Ilya Obridko, Ran Ginosar: Minimal Energy Asynchronous Dynamic Adders. IEEE Trans. VLSI Syst. 14(9): 1043-1047 (2006)
2005
33	EE	Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar: An Asynchronous Router for Multiple Service Levels Networks on Chip. ASYNC 2005: 44-53
32	EE	Tsachy Kapschitz, Ran Ginosar: Formal Verification of Synchronizers. CHARME 2005: 359-362
31	EE	Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Low-leakage repeaters for NoC interconnects. ISCAS (1) 2005: 600-603
30	EE	Ilya Obridko, Ran Ginosar: Low energy asynchronous architectures. ISCAS (5) 2005: 5238-5241
29	EE	Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar: Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. IEEE Trans. VLSI Syst. 13(4): 427-438 (2005)
2004
28	EE	Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou: Data Synchronization Issues in GALS SoCs. ASYNC 2004: 170-180
27	EE	Alex Branover, Rakefet Kol, Ran Ginosar: Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones. DATE 2004: 870-877
26	EE	Uri Frank, Ran Ginosar: A Predictive Synchronizer for Periodic Clock Domains. PATMOS 2004: 402-412
25	EE	Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar: Asynchronous gate-diffusion-input (GDI) circuits. IEEE Trans. VLSI Syst. 12(8): 847-856 (2004)
24	EE	Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Cost considerations in network on chip. Integration 38(1): 19-42 (2004)
23	EE	Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: QNoC: QoS architecture and design process for network on chip. Journal of Systems Architecture 50(2-3): 105-128 (2004)
2003
22	EE	Yaron Semiat, Ran Ginosar: Timing Measurements of Synchronization Circuits. ASYNC 2003: 68-77
21	EE	Ran Ginosar: Fourteen Ways to Fool Your Synchronizer. ASYNC 2003: 89-97
20	EE	Ken S. Stevens, Ran Ginosar, Shai Rotem: Relative timing [asynchronous design]. IEEE Trans. VLSI Syst. 11(1): 129-140 (2003)
19	EE	Y. Elboim, Avinoam Kolodny, Ran Ginosar: A clock-tuning circuit for system-on-chip. IEEE Trans. VLSI Syst. 11(4): 616-626 (2003)
1999
18	EE	Ken S. Stevens, Shai Rotem, Ran Ginosar: Relative Timing. ASYNC 1999: 208-218
17	EE	Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun: RAPPID: An Asynchronous Instruction Length Decoder. ASYNC 1999: 60-70
16	EE	Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken: CAD Directions for High Performance Asynchronous Circuits. DAC 1999: 116-121
1998
15	EE	Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun: Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. ASYNC 1998: 80-
14	EE	Uzi Zangi, Ran Ginosar: A low power video processor. ISLPED 1998: 136-138
13	EE	Rakefet Kol, Ran Ginosar: Kin: A High Performance Asynchronous Processor Architecture. International Conference on Supercomputing 1998: 433-440
1997
12		Rakefet Kol, Ran Ginosar: A Double-Latched Asynchronous Pipeline. ICCD 1997: 706-712
1993
11		Ilana David, Ran Ginosar, Michael Yoeli: Self-Timed Architecture of a Reduced Instruction Set Computer. Asynchronous Design Methodologies 1993: 29-43
10	EE	Alan Rotman, Ran Ginosar: Control unit synthesis from a high-level language. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 162-167 (1993)
1992
9		Ilana David, Ran Ginosar, Michael Yoeli: Implementing Sequential Machines as Self-Timed Circuits. IEEE Trans. Computers 41(1): 12-17 (1992)
8		Ilana David, Ran Ginosar, Michael Yoeli: An Efficient Implementation of Boolean Functions as Self-Timed Circuits. IEEE Trans. Computers 41(1): 2-11 (1992)
1991
7		Arie Harsat, Ran Ginosar: CARMEL-4: The Unify-Spawn Machine for FCP. ICLP 1991: 840-854
1990
6		Arie Harsat, Ran Ginosar: An Extended RISC Methodology and its Application to FCP. ICLP 1990: 67-82
1988
5		Arie Harsat, Ran Ginosar: CARMEL-2: A Second Generation VLSI Architecture for Flat Concurrent Prolog. FGCS 1988: 962-969
1985
4		Ran Ginosar, Dwight D. Hill: Design and Implementation of Switching Systems for Parallel Processors. ICPP 1985: 674-680
1982
3		Bruce W. Arden, Ran Ginosar: MP/C: A Multiprocessor/Computer Architecture. IEEE Trans. Computers 31(5): 455-473 (1982)
1981
2		Bruce W. Arden, Ran Ginosar: A Single-Relation Module for a Data Base Machine. ISCA 1981: 227-238
1		Bruce W. Arden, Ran Ginosar: MP/C: A Multiprocessor/Computer Architecture. ISCA 1981: 3-20

Coauthor Index

1	Boris Agapiev	[17]
2	Bruce W. Arden	[1] [2] [3]
3	Peter A. Beerel	[15] [17]
4	Ofer Binah	[39]
5	Evgeny Bolotin	[23] [24] [37] [42] [43]
6	Alex Branover	[27]
7	Steven M. Burns	[16]
8	Wei-Chun Chou	[15]
9	Israel Cidon	[23] [24] [31] [37] [40] [41] [42] [43]
10	Jordi Cortadella	[16]
11	Ilana David	[8] [9] [11]
12	Charles Dike	[17]
13	Rostislav (Reuven) Dobkin	[28] [29] [33] [35] [38] [40] [44] [45]
14	Y. Elboim	[19]
15	Jacob Erel	[39]
16	Uri Frank	[26] [36]
17	Eby G. Friedman	[46]
18	Eyal Friedman	[33]
19	Michael Glikson	[39]
20	Zvika Guz	[37] [42]
21	Arie Harsat	[5] [6] [7]
22	David L. Hayes	[39]
23	Dwight D. Hill	[4]
24	Tsachy Kapschitz	[32] [36]
25	Michael Kishinevsky	[16]
26	Rakefet Kol	[12] [13] [15] [17] [27]
27	Avinoam Kolodny	[19] [23] [24] [31] [37] [38] [41] [42] [43] [44] [45] [46]
28	Randy A. Lieberman	[39]
29	Tuvia Liran	[44]
30	Michael Moreinis	[25]
31	Arkadiy Morgenshtein	[25] [31] [45] [46]
32	Chris J. Myers	[15] [17]
33	Ilya Obridko	[30] [34]
34	Michael Peleg	[29]
35	Yevgeny Perelman	[44]
36	Rami Rom	[39]
37	Marly Roncken	[16] [17]
38	Kobi Rosenblum	[39]
39	Shai Rotem	[15] [16] [17] [18] [20]
40	Alan Rotman	[10]
41	Yaron Semiat	[22]
42	Christos P. Sotiriou	[28] [35]
43	Ken S. Stevens	[15] [16] [17] [18] [20]
44	Victoria Vishnyakov	[33]
45	Isask'har Walter	[37] [41]
46	Michael Yoeli	[8] [9] [11]
47	Kenneth Y. Yun	[15] [17]
48	Uzi Zangi	[14]

Colors in the list of coauthors