| 2007 |
|---|
| 14 | EE | Ryo Watanabe,
Masaaki Kondo,
Masashi Imai,
Hiroshi Nakamura,
Takashi Nanya:
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC.
DATE 2007: 797-802 |
| 2006 |
|---|
| 13 | EE | Masashi Imai,
Takashi Nanya:
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations.
ASYNC 2006: 68-77 |
| 12 | EE | Kouichi Watanabe,
Masashi Imai,
Masaaki Kondo,
Hiroshi Nakamura,
Takashi Nanya:
Design Method of High Performance and Low Power Functional Units Considering Delay Variations.
IEICE Transactions 89-A(12): 3519-3528 (2006) |
| 2004 |
|---|
| 11 | EE | Masashi Imai,
Metehan Özcan,
Takashi Nanya:
Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model.
ASYNC 2004: 62-71 |
| 10 | EE | Masayuki Tsukisaka,
Masashi Imai,
Takashi Nanya:
Asynchronous Scan-Latch controller for Low Area Overhead DFT.
ICCD 2004: 66-71 |
| 9 | EE | Hiroshi Nakamura,
Takuro Hayashida,
Masaaki Kondo,
Yuya Tajima,
Masashi Imai,
Takashi Nanya:
Skewed Checkpointing for Tolerating Multi-Node Failures.
SRDS 2004: 116-125 |
| 2003 |
|---|
| 8 | EE | Hiroshi Saito,
Euiseok Kim,
Nattha Sretasereekul,
Masashi Imai,
Hiroshi Nakamura,
Takashi Nanya:
Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions.
ASYNC 2003: 184-195 |
| 7 | EE | Nattha Sretasereekul,
Hiroshi Saito,
Masashi Imai,
Euiseok Kim,
Metehan Özcan,
K. Thongnoo,
Hiroshi Nakamura,
Takashi Nanya:
A zero-time-overhead asynchronous four-phase controller.
ISCAS (5) 2003: 205-208 |
| 6 | EE | Hiroshi Saito,
Euiseok Kim,
Masashi Imai,
Nattha Sretasereekul,
Hiroshi Nakamura,
Takashi Nanya:
Control signal sharing of asynchronous circuits using datapath delay information.
ISCAS (5) 2003: 617-620 |
| 2002 |
|---|
| 5 | EE | Metehan Özcan,
Masashi Imai,
Takashi Nanya:
Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits.
ASYNC 2002: 109-114 |
| 4 | | Masayuki Tsukisaka,
Masashi Imai,
Takashi Nanya:
High Throughput Asynchronous Domino Using Dual output Buffer.
IWLS 2002: 279-282 |
| 2001 |
|---|
| 3 | EE | Motokazu Ozawa,
Masashi Imai,
Hiroshi Nakamura,
Takashi Nanya,
Yoichiro Ueno:
Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors.
ASYNC 2001: 162-172 |
| 1998 |
|---|
| 2 | | Akihiro Takamura,
Motokazu Ozawa,
Izumi Fukasaku,
Taro Fujii,
Yoichiro Ueno,
Masashi Imai,
Masashi Kuwako,
Takashi Nanya:
TITAC-2: An Asynchronous 32-bit Microprocessor.
ASP-DAC 1998: 319-320 |
| 1997 |
|---|
| 1 | | Akihiro Takamura,
Masashi Kuwako,
Masashi Imai,
Taro Fujii,
Motokazu Ozawa,
Izumi Fukasaku,
Yoichiro Ueno,
Takashi Nanya:
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model.
ICCD 1997: 288-294 |
