Rainer Laur

2007
15	EE	Hans Georg Brachtendorf, Angelika Bunse-Gerstner, Barbara Lang, Rainer Laur: An inverse method of characteristics for analyzing circuits with widely separated time-scales. ISCAS 2007: 509-512
14	EE	S.-P. Vudathu, Kishore K. Duganapalli, Rainer Laur, D. Kubalinska, Angelika Bunse-Gerstner: Parametric Yield Analysis of Mems via Statistical Methods CoRR abs/0711.3287: (2007)
2005
13		Christian Gorecki, Christian Behrens, Rainer Laur: A new approach towards authenticated key agreement schemes for resource-constrained devices. GI Jahrestagung (2) 2005: 155-157
2002
12	EE	Hans Georg Brachtendorf, S. Lampe, Rainer Laur, Robert C. Melville, Peter Feldmann: Steady State Calculation of Oscillators Using Continuation Methods. DATE 2002: 1139
2000
11	EE	Hans Georg Brachtendorf, Rainer Laur: An accurate model for the transient simulation of lossy interconnects based on a novel discretization formula. Integration 29(2): 117-129 (2000)
1999
10	EE	Christoph Jäschke, Rainer Laur, Friedrich Beckmann: Time Constrained Modulo Scheduling with Global Resource Sharing. DATE 1999: 210-216
1998
9	EE	Christoph Jäschke, Rainer Laur: Resource Constrained Modulo Scheduling with Global Resource Sharing. ISSS 1998: 60-65
1995
8		Hans Georg Brachtendorf, G. Welsch, Rainer Laur: Fast Simulation of the Steady-State of Circuits by the Harmonic Balance Technique. ISCAS 1995: 1388-1391
7		Stefan Wolter, Holger Matz, Andreas Schubert, Rainer Laur: On the VLSI Implementation of the International Data Encryption Algorithm IDEA. ISCAS 1995: 397-400
6		Stefan Honken, Feng-Ming Yang, Rainer Laur: A HDTV-Suited Architecture for a Fast Full Search Block-Matching Algorithm. ISCAS 1995: 621-624
1994
5		Hans Georg Brachtendorf, Rainer Laur: Modeling of Frequency-dependent Hysteresis with SPICE. ISCAS 1994: 343-346
4		Beom-Ik Cheon, Walter Anheier, Rainer Laur: A New Strategy for Test Pattern Generation in Sequential Circuits. ISCAS 1994: 77-80
3		Feng-Ming Yang, Stefan Wolter, Rainer Laur: VLSI Architecture for HDTV Motion Estimation Based on Block-Matching Algorithm. VLSI Design 1994: 287-290
1993
2		Stefan Wolter, Andreas Schubert, Holger Matz, Rainer Laur: On the Comparison Between Architectures for the Implementation of Distributed Arithmetic. ISCAS 1993: 1829-1832
1982
1	EE	Walter L. Engl, Rainer Laur, Heinz K. Dirks: MEDUSA - A Simulator for Modular Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 1(2): 85-93 (1982)

Coauthor Index

1	Walter Anheier	[4]
2	Friedrich Beckmann	[10]
3	Christian Behrens	[13]
4	Hans Georg Brachtendorf	[5] [8] [11] [12] [15]
5	Angelika Bunse-Gerstner	[14] [15]
6	Beom-Ik Cheon	[4]
7	Heinz K. Dirks	[1]
8	Kishore K. Duganapalli	[14]
9	Walter L. Engl	[1]
10	Peter Feldmann	[12]
11	Christian Gorecki	[13]
12	Stefan Honken	[6]
13	Christoph Jäschke	[9] [10]
14	D. Kubalinska	[14]
15	S. Lampe	[12]
16	Barbara Lang	[15]
17	Holger Matz	[2] [7]
18	Robert C. Melville	[12]
19	Andreas Schubert	[2] [7]
20	S.-P. Vudathu	[14]
21	G. Welsch	[8]
22	Stefan Wolter	[2] [3] [7]
23	Feng-Ming Yang	[3] [6]

Colors in the list of coauthors