Saibal Mukhopadhyay

2008
43	EE	Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy: Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design 2008: 125-130
42	EE	Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy: Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. VTS 2008: 101-106
41	EE	Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy: Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 174-183 (2008)
2007
40		Saibal Mukhopadhyay, Qikai Chen, Kaushik Roy: Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance. DDECS 2007: 69-74
39	EE	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang: Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. ISLPED 2007: 20-25
38	EE	Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: Process Variations and Process-Tolerant Design. VLSI Design 2007: 699-704
37	EE	Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy: Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies CoRR abs/0710.4663: (2007)
36	EE	Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits CoRR abs/0710.4729: (2007)
35	EE	Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectronics Journal 38(8-9): 931-941 (2007)
2006
34	EE	Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy: Speed binning aware design methodology to improve profit under parameter variations. ASP-DAC 2006: 712-717
33	EE	Swaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, Kaushik Roy: Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. DAC 2006: 971-976
32	EE	Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy: Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. DATE 2006: 983-988
31	EE	Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design 2006: 445-452
30	EE	Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim: Leakage Power Analysis and Reduction for Nanoscale Circuits. IEEE Micro 26(2): 68-80 (2006)
29	EE	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. IEEE Trans. VLSI Syst. 14(2): 183-192 (2006)
28	EE	Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2427-2436 (2006)
27	EE	Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1486-1495 (2006)
2005
26	EE	Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. Asian Test Symposium 2005: 170-175
25	EE	Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy: Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. Asian Test Symposium 2005: 176-181
24	EE	Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. DATE 2005: 224-229
23	EE	Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy: Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. DATE 2005: 926-931
22		Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-gate SOI devices for low-power and high-performance applications. ICCAD 2005: 217-224
21	EE	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy: A Feasibility Study of Subthreshold SRAM Across Technology Generations. ICCD 2005: 417-424
20	EE	Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy: Process Variation Tolerant Online Current Monitor for Robust Systems. IOLTS 2005: 171-176
19	EE	Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. IOLTS 2005: 275-280
18	EE	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy: Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. ISLPED 2005: 8-13
17	EE	Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED 2005: 410-415
16	EE	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. ISQED 2005: 490-495
15	EE	Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy: A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans. VLSI Syst. 13(3): 349-357 (2005)
14	EE	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy: Low-power scan design using first-level supply gating. IEEE Trans. VLSI Syst. 13(3): 384-395 (2005)
13	EE	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1859-1880 (2005)
12	EE	Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy: Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 363-381 (2005)
2004
11	EE	Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy: Leakage in nano-scale technologies: mechanisms, impact and design considerations. DAC 2004: 6-11
10	EE	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Statistical design and optimization of SRAM cell for yield enhancement. ICCAD 2004: 10-13
9	EE	Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy: A Novel Low-Power Scan Design Technique Using Supply Gating. ICCD 2004: 60-65
8	EE	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy: Modeling and Estimation of Leakage in Sub-90nm Devices. VLSI Design 2004: 65-
7	EE	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy: A circuit-compatible model of ballistic carbon nanotube field-effect transistors. IEEE Trans. on CAD of Integrated Circuits and Systems 23(10): 1411-1420 (2004)
2003
6	EE	Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy: Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. DAC 2003: 169-174
5	EE	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy: Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation. ICCAD 2003: 487-490
4	EE	Saibal Mukhopadhyay, Kaushik Roy: Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation. ISLPED 2003: 172-175
3	EE	Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy: A forward body-biased low-leakage SRAM cache: device and architecture considerations. ISLPED 2003: 6-9
2	EE	Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy: Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. VLSI Syst. 11(4): 716-730 (2003)
2002
1	EE	Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand: Leakage Current in Deep-Submicron CMOS Circuits. Journal of Circuits, Systems, and Computers 11(6): 575-600 (2002)

Coauthor Index

1	Amit Agarwal	[2] [11] [30]
2	Hari Ananthan	[22] [31]
3	Nilanjan Banerjee	[23] [37]
4	Aditya Bansal	[22] [31] [32] [43]
5	Swarup Bhunia	[9] [14] [19] [23] [24] [26] [27] [28] [34] [36] [37] [38]
6	R. T. Cakici	[2]
7	Tamer Cakici	[22] [31]
8	Qikai Chen	[20] [32] [40]
9	Jung Hwan Choi	[34]
10	Ching-Te Chuang	[17] [18] [35] [39] [42] [43]
11	Animesh Datta	[19] [23] [26] [28] [34] [37]
12	Debjyoti Ghosh	[9] [14]
13	Swaroop Ghosh	[33]
14	Rajiv V. Joshi	[17] [35]
15	Chris H. Kim	[2] [3] [11] [15] [30]
16	Jae-Joon Kim	[3] [15] [17] [35] [42] [43]
17	Kee-Jong Kim	[33]
18	Keunwoo Kim	[17] [18] [35] [39] [43]
19	Shih-Hsien Lo	[17] [35]
20	Hamid Mahmoodi	[20] [41]
21	Hamid Mahmoodi-Meimand	[1] [9] [10] [13] [14] [16] [22] [25] [29] [31]
22	Niladri Narayan Mojumder	[42]
23	Cassondra Neau	[2]
24	Arijit Raychowdhury	[5] [6] [7] [8] [12] [21] [25] [30]
25	Kaushik Roy	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [40] [41] [42] [43]