| 2008 |
|---|
| 153 | EE | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Alex Orailoglu,
Hideo Fujiwara:
Scheduling Power-Constrained Tests through the SoC Functional Bus.
IEICE Transactions 91-D(3): 736-746 (2008) |
| 2007 |
|---|
| 152 | EE | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Alex Orailoglu,
Hideo Fujiwara:
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses.
ASP-DAC 2007: 720-725 |
| 151 | EE | Chengmo Yang,
Alex Orailoglu:
Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs.
CASES 2007: 150-154 |
| 150 | EE | Chengmo Yang,
Alex Orailoglu:
Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules.
CODES+ISSS 2007: 15-20 |
| 149 | EE | Wenjing Rao,
Alex Orailoglu,
Ramesh Karri:
Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs.
DATE 2007: 865-869 |
| 148 | EE | Wenjing Rao,
Alex Orailoglu,
Ramesh Karri:
Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays.
DSN 2007: 216-224 |
| 147 | EE | R. Iris Bahar,
Dan W. Hammerstrom,
Justin E. Harlow III,
William H. Joyner Jr.,
Clifford Lau,
Diana Marculescu,
Alex Orailoglu,
Massoud Pedram:
Architectures for Silicon Nanoelectronics and Beyond.
IEEE Computer 40(1): 25-33 (2007) |
| 146 | EE | Yiorgos Makris,
Alex Orailoglu:
On the identification of modular test requirements for low cost hierarchical test path construction.
Integration 40(3): 315-325 (2007) |
| 145 | EE | Peter Petrov,
Alex Orailoglu:
Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory.
International Journal of Parallel Programming 35(2): 157-177 (2007) |
| 144 | EE | Wenjing Rao,
Alex Orailoglu,
Ramesh Karri:
Towards Nanoelectronics Processor Architectures.
J. Electronic Testing 23(2-3): 235-254 (2007) |
| 2006 |
|---|
| 143 | EE | Chengmo Yang,
Alex Orailoglu:
Power efficient branch prediction through early identification of branch addresses.
CASES 2006: 169-178 |
| 142 | EE | Wenjing Rao,
Alex Orailoglu,
Ramesh Karri:
Topology aware mapping of logic functions onto nanowire-based crossbar architectures.
DAC 2006: 723-726 |
| 141 | EE | Wenjing Rao,
Alex Orailoglu,
Ramesh Karri:
Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics.
European Test Symposium 2006: 63-68 |
| 140 | EE | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Alex Orailoglu,
Hideo Fujiwara:
Power-Constrained SOC Test Schedules through Utilization of Functional Buses.
ICCD 2006 |
| 139 | EE | Chengmo Yang,
Alex Orailoglu:
Power-efficient instruction delivery through trace reuse.
PACT 2006: 192-201 |
| 138 | EE | Wenjing Rao,
Alex Orailoglu,
Ramesh Karri:
Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance.
VTS 2006: 214-221 |
| 137 | EE | Mingjing Chen,
Hosam Haggag,
Alex Orailoglu:
Decision Tree Based Mismatch Diagnosis in Analog Circuits.
VTS 2006: 278-285 |
| 2005 |
|---|
| 136 | | Carlos Galup-Montoro,
Sergio Bampi,
Alex Orailoglu:
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005
ACM 2005 |
| 135 | EE | Tongquan Wei,
Kaijie Wu,
Ramesh Karri,
Alex Orailoglu:
Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands.
ASP-DAC 2005: 1192-1195 |
| 134 | EE | Rasit Onur Topaloglu,
Alex Orailoglu:
Forward discrete probability propagation method for device performance characterization under process variations.
ASP-DAC 2005: 220-223 |
| 133 | EE | Wenjing Rao,
Alex Orailoglu,
Ramesh Karri:
Fault tolerant nanoelectronic processor architectures.
ASP-DAC 2005: 311-316 |
| 132 | EE | Raid Ayoub,
Alex Orailoglu:
A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses.
ASP-DAC 2005: 729-734 |
| 131 | EE | Peter Petrov,
Daniel Tracy,
Alex Orailoglu:
Energy-effcient physically tagged caches for embedded processors with virtual memory.
DAC 2005: 17-22 |
| 130 | EE | Rasit Onur Topaloglu,
Alex Orailoglu:
A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs.
DAC 2005: 851-856 |
| 129 | EE | Wenjing Rao,
Alex Orailoglu,
Ramesh Karri:
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors.
ICCD 2005: 533-542 |
| 128 | EE | Peter Petrov,
Alex Orailoglu:
A reprogrammable customization framework for efficient branch resolution in embedded processors.
ACM Trans. Embedded Comput. Syst. 4(2): 452-468 (2005) |
| 127 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations.
IEEE Trans. Computers 54(1): 61-75 (2005) |
| 126 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Test power reductions through computationally efficient, decoupled scan chain modifications.
IEEE Transactions on Reliability 54(2): 215-223 (2005) |
| 125 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Efficient RT-Level Fault Diagnosis.
J. Comput. Sci. Technol. 20(2): 166-174 (2005) |
| 2004 |
|---|
| 124 | | Alex Orailoglu,
Pai H. Chou,
Petru Eles,
Axel Jantsch:
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004
ACM 2004 |
| 123 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Efficient RT-level fault diagnosis methodology.
ASP-DAC 2004: 212-217 |
| 122 | EE | Rasit Onur Topaloglu,
Alex Orailoglu:
On mismatch in the deep sub-micron era - from physics to circuits.
ASP-DAC 2004: 62-67 |
| 121 | EE | Baris Arslan,
Alex Orailoglu:
CircularScan: A Scan Architecture for Test Cost Reduction.
DATE 2004: 1290-1295 |
| 120 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Scan Power Minimization through Stimulus and Response Transformations.
DATE 2004: 404-409 |
| 119 | EE | Wenjing Rao,
Alex Orailoglu,
G. Su:
Frugal linear network-based test decompression for drastic test cost reductions.
ICCAD 2004: 721-725 |
| 118 | EE | Baris Arslan,
Alex Orailoglu:
Design space exploration for aggressive test cost reduction in CircularScan architectures.
ICCAD 2004: 726-731 |
| 117 | EE | Baris Arslan,
Ozgur Sinanoglu,
Alex Orailoglu:
Extending the Applicability of Parallel-Serial Scan Designs.
ICCD 2004: 200-203 |
| 116 | EE | Sule Ozev,
Alex Orailoglu:
End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths.
ICCD 2004: 72-77 |
| 115 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Autonomous Yet Deterministic Test of SOC Cores.
ITC 2004: 1359-1368 |
| 114 | EE | Wenjing Rao,
Alex Orailoglu,
Ramesh Karri:
Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems.
ITC 2004: 472-478 |
| 113 | EE | Baris Arslan,
Alex Orailoglu:
Test Cost Reduction Through A Reconfigurable Scan Architecture.
ITC 2004: 945-952 |
| 112 | EE | Sule Ozev,
Ismet Bayraktaroglu,
Alex Orailoglu:
Seamless Test of Digital Components in Mixed-Signal Paths.
IEEE Design & Test of Computers 21(1): 44-55 (2004) |
| 111 | EE | Peter Petrov,
Alex Orailoglu:
Transforming Binary Code for Low-Power Embedded Processors.
IEEE Micro 24(3): 21-33 (2004) |
| 110 | EE | Sule Ozev,
Alex Orailoglu:
Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead.
IEEE Trans. VLSI Syst. 12(7): 756-765 (2004) |
| 109 | EE | Peter Petrov,
Alex Orailoglu:
Low-power instruction bus encoding for embedded processors.
IEEE Trans. VLSI Syst. 12(8): 812-826 (2004) |
| 108 | EE | Peter Petrov,
Alex Orailoglu:
Tag compression for low power in dynamically customizable embedded processors.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1031-1047 (2004) |
| 107 | EE | Yiorgos Makris,
Ismet Bayraktaroglu,
Alex Orailoglu:
Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test.
IEEE Transactions on Reliability 53(2): 269-278 (2004) |
| 106 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Fast and energy-frugal deterministic test through efficient compression and compaction techniques.
Journal of Systems Architecture 50(5): 257-266 (2004) |
| 2003 |
|---|
| 105 | | Rajesh Gupta,
Yukihiro Nakamura,
Alex Orailoglu,
Pai H. Chou:
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003
ACM 2003 |
| 104 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test.
Asian Test Symposium 2003: 202-209 |
| 103 | EE | Baris Arslan,
Alex Orailoglu:
Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information.
Asian Test Symposium 2003: 230-235 |
| 102 | EE | Wenjing Rao,
Ismet Bayraktaroglu,
Alex Orailoglu:
Test application time and volume compression through seed overlapping.
DAC 2003: 732-737 |
| 101 | EE | Peter Petrov,
Alex Orailoglu:
Power Efficiency through Application-Specific Instruction Memory Transformations.
DATE 2003: 10030-10035 |
| 100 | EE | Wenjing Rao,
Alex Orailoglu:
Virtual Compression through Test Vector Stitching for Scan Based Designs.
DATE 2003: 10104-10109 |
| 99 | EE | Peter Petrov,
Alex Orailoglu:
Low-power Branch Target Buffer for Application-Specific Embedded Processors.
DSD 2003: 158-165 |
| 98 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Hierarchical Constraint Conscious RT-level Test Generation.
DSD 2003: 312-318 |
| 97 | EE | Peter Petrov,
Alex Orailoglu:
Customizable Embedded Processor Architectures.
DSD 2003: 468-475 |
| 96 | EE | Peter Petrov,
Alex Orailoglu:
Compiler-Based Register Name Adjustment for Low-Power Embedded Processors.
ICCAD 2003: 523-528 |
| 95 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Partial Core Encryption for Performance-Efficient Test of SOCs.
ICCAD 2003: 91-94 |
| 94 | EE | Peter Petrov,
Alex Orailoglu:
Virtual Page Tag Reduction for Low-power TLBs.
ICCD 2003: 371-374 |
| 93 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Aggressive Test Power Reduction Through Test Stimuli Transformation.
ICCD 2003: 542-547 |
| 92 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Modeling Scan Chain Modifications For Scan-in Test Power Minimization.
ITC 2003: 602-611 |
| 91 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression.
VTS 2003: 113-120 |
| 90 | EE | Peter Petrov,
Alex Orailoglu:
Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors.
IEEE Design & Test of Computers 20(1): 18-25 (2003) |
| 89 | | Alex Orailoglu,
Alexander V. Veidenbaum:
Guest Editors' Introduction: Application-Specific Microprocessors.
IEEE Design & Test of Computers 20(1): 6-7 (2003) |
| 88 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Compacting Test Responses for Deeply Embedded SoC Cores.
IEEE Design & Test of Computers 20(4): 22-30 (2003) |
| 87 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs.
IEEE Trans. Computers 52(11): 1480-1489 (2003) |
| 86 | EE | Alex Orailoglu:
Guest Editor's Introduction.
International Journal of Parallel Programming 31(6): 407-409 (2003) |
| 2002 |
|---|
| 85 | EE | Yiorgos Makris,
Alex Orailoglu:
Test Requirement Analysis for Low Cost Hierarchical Test Path Construction.
Asian Test Symposium 2002: 134-139 |
| 84 | EE | Peter Petrov,
Alex Orailoglu:
Energy frugal tags in reprogrammable I-caches for application-specific embedded processors.
CODES 2002: 181-186 |
| 83 | EE | Peter Petrov,
Alex Orailoglu:
Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches.
DATE 2002: 1065-1071 |
| 82 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Gate Level Fault Diagnosis in Scan-Based BIST.
DATE 2002: 376-381 |
| 81 | EE | Sherief Reda,
Alex Orailoglu:
Reducing Test Application Time Through Test Data Mutation Encoding.
DATE 2002: 387-395 |
| 80 | EE | Érika F. Cota,
Luigi Carro,
Marcelo Lubaszewski,
Alex Orailoglu:
Test Planning and Design Space Exploration in a Core-Based Environment.
DATE 2002: 478-485 |
| 79 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation.
DFT 2002: 325-333 |
| 78 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
A novel scan architecture for power-efficient, rapid test.
ICCAD 2002: 299-303 |
| 77 | EE | Sule Ozev,
Alex Orailoglu:
Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits.
ICCD 2002: 258-264 |
| 76 | EE | Baris Arslan,
Alex Orailoglu:
Fault Dictionary Size Reduction through Test Response Superposition.
ICCD 2002: 480- |
| 75 | EE | Sule Ozev,
Alex Orailoglu,
Hosam Haggag:
Automated test development and test time reduction for RF subsystems.
ISCAS (1) 2002: 581-584 |
| 74 | EE | Sule Ozev,
Alex Orailoglu:
An Integrated Tool for Analog Test Generation and Fault Simulation.
ISQED 2002: 267-272 |
| 73 | EE | Sherief Reda,
Rolf Drechsler,
Alex Orailoglu:
On the Relation between SAT and BDDs for Equivalence Checking.
ISQED 2002: 394-399 |
| 72 | EE | Alex Orailoglu,
Peter Petrov:
Low-Power Data Memory Communication for Application-Specific Embedded Processors.
ISSS 2002: 219-224 |
| 71 | EE | Ozgur Sinanoglu,
Ismet Bayraktaroglu,
Alex Orailoglu:
Scan Power Reduction Through Test Data Transition Frequency Analysis.
ITC 2002: 844-850 |
| 70 | EE | Ozgur Sinanoglu,
Ismet Bayraktaroglu,
Alex Orailoglu:
Test Power Reduction through Minimization of Scan Chain Transitions.
VTS 2002: 166-172 |
| 69 | EE | Sule Ozev,
Alex Orailoglu:
Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis.
VTS 2002: 213-222 |
| 68 | EE | Laurence Goodby,
Alex Orailoglu,
Paul M. Chau:
Microarchitectural synthesis of performance-constrained, low-power VLSI designs.
ACM Trans. Design Autom. Electr. Syst. 7(1): 122-136 (2002) |
| 67 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST.
IEEE Design & Test of Computers 19(1): 42-53 (2002) |
| 66 | EE | Sule Ozev,
Christian Olgaard,
Alex Orailoglu:
Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers.
IEEE Design & Test of Computers 19(5): 82-91 (2002) |
| 65 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Efficient Construction of Aliasing-Free Compaction Circuitry.
IEEE Micro 22(5): 82-92 (2002) |
| 2001 |
|---|
| 64 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Compaction Schemes with Minimum Test Application Time.
Asian Test Symposium 2001: 199-204 |
| 63 | EE | Sobeeh Almukhaizim,
Peter Petrov,
Alex Orailoglu:
Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit.
Asian Test Symposium 2001: 319-324 |
| 62 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck?
Asian Test Symposium 2001: 373-378 |
| 61 | EE | Peter Petrov,
Alex Orailoglu:
Towards effective embedded processors in codesigns: customizable partitioned caches.
CODES 2001: 79-84 |
| 60 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Test Volume and Application Time Reduction Through Scan Chain Concealment.
DAC 2001: 151-155 |
| 59 | EE | Peter Petrov,
Alex Orailoglu:
Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors.
DAC 2001: 512-517 |
| 58 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Diagnosis for scan-based BIST: reaching deep into the signatures.
DATE 2001: 102-111 |
| 57 | | Peter Petrov,
Alex Orailoglu:
Data cache energy minimizations through programmable tag size matching to the applications.
ISSS 2001: 113-117 |
| 56 | | Ozgur Sinanoglu,
Alex Orailoglu:
Space and time compaction schemes for embedded cores.
ITC 2001: 521-529 |
| 55 | | Christian Olgaard,
Sule Ozev,
Alex Orailoglu:
Testability implications in low-cost integrated radio transceivers: a Bluetooth case study.
ITC 2001: 965-974 |
| 54 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
RT-level Fault Simulation Based on Symbolic Propagation.
VTS 2001: 240-245 |
| 53 | EE | Yiorgos Makris,
Vishal Patel,
Alex Orailoglu:
Efficient Transparency Extraction and Utilization in Hierarchical Test.
VTS 2001: 246-251 |
| 52 | EE | Peter Petrov,
Alex Orailoglu:
Performance and power effectiveness in embedded processors customizable partitioned caches.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1309-1318 (2001) |
| 51 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Concurrent test for digital linear systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1132-1142 (2001) |
| 2000 |
|---|
| 50 | EE | Yiorgos Makris,
Jamison Collins,
Alex Orailoglu:
Fast hierarchical test path construction for DFT-free controller-datapath circuits.
Asian Test Symposium 2000: 185-190 |
| 49 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Accumulation-based concurrent fault detection for linear digital state variable systems.
Asian Test Symposium 2000: 484- |
| 48 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Improved fault diagnosis in scan-based BIST via superposition.
DAC 2000: 55-58 |
| 47 | EE | Sule Ozev,
Ismet Bayraktaroglu,
Alex Orailoglu:
Test Synthesis for Mixed-Signal SOC Paths.
DATE 2000: 128-133 |
| 46 | EE | Laurence Goodby,
Alex Orailoglu:
Test Quality and Fault Risk in Digital Filter Datapath BIST.
DATE 2000: 468-475 |
| 45 | | Ismet Bayraktaroglu,
Alex Orailoglu:
Deterministic partitioning techniques for fault diagnosis in scan-based BIST.
ITC 2000: 273-282 |
| 44 | EE | Sule Ozev,
Alex Orailoglu:
Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems.
VTS 2000: 149-156 |
| 43 | EE | Yiorgos Makris,
Ismet Bayraktaroglu,
Alex Orailoglu:
Invariance-Based On-Line Test for RTL Controller-Datapath Circuits.
VTS 2000: 459-464 |
| 42 | EE | Samuel Norman Hamilton,
Alex Orailoglu:
On-line test for fault-secure fault identification.
IEEE Trans. VLSI Syst. 8(4): 446-452 (2000) |
| 1999 |
|---|
| 41 | EE | Yiorgos Makris,
Alex Orailoglu:
Channel-Based Behavioral Test Synthesis for Improved Module Reachability.
DATE 1999: 283-288 |
| 40 | EE | Samuel Norman Hamilton,
Alex Orailoglu,
Andre Hertwig:
Self Recovering Controller and Datapath Codesign.
DATE 1999: 596-601 |
| 39 | EE | Sule Ozev,
Alex Orailoglu:
Low-Cost Test for Large Analog IC's.
DFT 1999: 101- |
| 38 | EE | Yiorgos Makris,
Alex Orailoglu:
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths.
DFT 1999: 339-347 |
| 37 | EE | Ismet Bayraktaroglu,
Alex Orailoglu:
Low-Cost On-Line Test for Digital Filters.
VTS 1999: 446-451 |
| 36 | EE | Laurence Goodby,
Alex Orailoglu:
Redundancy and testability in digital filter datapaths.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 631-644 (1999) |
| 1998 |
|---|
| 35 | EE | Ismet Bayraktaroglu,
K. Udawatta,
Alex Orailoglu:
An Examination of PRPG Selection Approaches for Large, Industrial Designs.
Asian Test Symposium 1998: 440- |
| 34 | EE | Samuel Norman Hamilton,
Alex Orailoglu:
Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs.
DATE 1998: 604- |
| 33 | EE | Samuel Norman Hamilton,
Alex Orailoglu:
Transient and Intermittent Fault Recovery without Rollback.
DFT 1998: 252-260 |
| 32 | EE | Alex Orailoglu:
Graceful Degradation in Synthesis of VLSI ICs.
DFT 1998: 301-311 |
| 31 | EE | Yiorgos Makris,
Alex Orailoglu:
DFT guidance through RTL test justification and propagation analysis.
ITC 1998: 668- |
| 30 | EE | Samuel Norman Hamilton,
Alex Orailoglu:
Efficient Self-Recovering ASIC Design.
IEEE Design & Test of Computers 15(4): 25-35 (1998) |
| 1997 |
|---|
| 29 | EE | Laurence Goodby,
Alex Orailoglu:
Frequency-Domain Compatibility in Digital Filter BIST.
DAC 1997: 540-545 |
| 28 | | Samuel Norman Hamilton,
Alex Orailoglu:
Microarchitectural Synthesis of ICs with Embedded Concurrent Fault Isolation.
FTCS 1997: 329-338 |
| 27 | EE | Alex Orailoglu:
Microarchitectural synthesis for rapid BIST testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 573-586 (1997) |
| 1996 |
|---|
| 26 | EE | Laurence Goodby,
Alex Orailoglu:
Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths.
DAC 1996: 813-818 |
| 25 | EE | Alex Orailoglu:
Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs.
ICCD 1996: 112-117 |
| 24 | EE | R. L. Campbell,
P. Kuekes,
David Y. Lepejian,
W. Maly,
Michael Nicolaidis,
Alex Orailoglu:
Can Defect-Tolerant Chips Better Meet the Quality Challenge?
VTS 1996: 362-363 |
| 23 | EE | Ramesh Karri,
Karin Högstedt,
Alex Orailoglu:
Computer-Aided Design of Fault-Tolerant VLSI Systems.
IEEE Design & Test of Computers 13(3): 88-96 (1996) |
| 22 | | Alex Orailoglu,
Ramesh Karri:
Automatic Synthesis of Self-Recovering VLSI Systems.
IEEE Trans. Computers 45(2): 131-142 (1996) |
| 1995 |
|---|
| 21 | EE | Mahsa Vahidi,
Alex Orailoglu:
Metric-based transformations for self testable VLSI designs with high test concurrency.
EURO-DAC 1995: 136-141 |
| 20 | | Laurence Goodby,
Alex Orailoglu:
Towards 100% Testable FIR Digital Filters.
ITC 1995: 394-402 |
| 19 | EE | Mahsa Vahidi,
Alex Orailoglu:
Testability metrics for synthesis of self-testable designs and effective test plans.
VTS 1995: 170-175 |
| 1994 |
|---|
| 18 | EE | Ian G. Harris,
Alex Orailoglu:
Microarchitectural Synthesis of VLSI Designs with High Test Concurrency.
DAC 1994: 206-211 |
| 17 | EE | Ramesh Karri,
Alex Orailoglu:
Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis.
DAC 1994: 552-556 |
| 16 | | Ian G. Harris,
Alex Orailoglu:
Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST.
EDAC-ETC-EUROASIC 1994: 119-123 |
| 15 | | Ian G. Harris,
Alex Orailoglu:
SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability.
ICCD 1994: 101-104 |
| 14 | | Laurence Goodby,
Alex Orailoglu,
Paul M. Chau:
Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs.
ICCD 1994: 323-326 |
| 13 | | Karin Högstedt,
Alex Orailoglu:
Integrating Binding Constraints in the Synthesis of Area-Efficient Self-Recovering Microarchitectures.
ICCD 1994: 331-334 |
| 12 | EE | Alex Orailoglu,
Ramesh Karri:
Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures.
IEEE Trans. VLSI Syst. 2(3): 304-311 (1994) |
| 11 | EE | Alex Orailoglu,
Ramesh Karri:
Synthesis of fault-tolerant and real-time microarchitectures.
Journal of Systems and Software 25(1): 73-84 (1994) |
| 1993 |
|---|
| 10 | EE | Ramesh Karri,
Alex Orailoglu:
High-Level Synthesis of Fault-Secure Microarchitectures.
DAC 1993: 429-433 |
| 9 | | Ramesh Karri,
Alex Orailoglu:
Optimal Self-Recovering Microarchitecture Synthesis.
FTCS 1993: 512-521 |
| 8 | | Alex Orailoglu,
Ian G. Harris:
Test Path Generation and Test Scheduling for Self-Testable Designs.
ICCD 1993: 528-531 |
| 7 | | Ian G. Harris,
Alex Orailoglu:
Intertwined Scheduling, Module Selection and Allocation in Time-and-Area.
ISCAS 1993: 1682-1685 |
| 1992 |
|---|
| 6 | EE | Ramesh Karri,
Alex Orailoglu:
Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs.
DAC 1992: 662-665 |
| 5 | | Ramesh Karri,
Alex Orailoglu:
Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs.
FTCS 1992: 519-526 |
| 4 | | Alex Orailoglu,
Ramesh Karri:
High-Level Synthesis of Self-Recovering MicroArchitectures.
ICCD 1992: 286-289 |
| 1991 |
|---|
| 3 | EE | Ramesh Karri,
Alex Orailoglu:
ALPS: An Algorithm for Pipeline Data Path Synthesis.
MICRO 1991: 124-132 |
| 2 | EE | Amir K. Hekmatpour,
Alex Orailoglu,
Paul M. Chau:
Hierarchical Modeling of the VLSI Design Process.
IEEE Expert 6(2): 56-70 (1991) |
| 1986 |
|---|
| 1 | EE | Alex Orailoglu,
Daniel Gajski:
Flow graph representation.
DAC 1986: 503-509 |
