| 1998 |
|---|
| 9 | EE | Satyamurthy Pullela,
Rajendran Panda,
Abhijit Dharchoudhury,
Gopal Vija:
CMOS Combinational Circuit Sizing by Stage-wise Tapering.
DATE 1998: 985-988 |
| 1997 |
|---|
| 8 | EE | Sergey Gavrilov,
Alexey Glebov,
Satyamurthy Pullela,
S. C. Moore,
Abhijit Dharchoudhury,
Rajendran Panda,
G. Vijayan,
David Blaauw:
Library-less synthesis for static CMOS combinational logic circuits.
ICCAD 1997: 658-662 |
| 7 | | Abhijit Dharchoudhury,
David Blaauw,
Joe Norton,
Satyamurthy Pullela,
J. Dunning:
Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor.
ICCD 1997: 143-148 |
| 6 | EE | Satyamurthy Pullela,
Noel Menezes,
Lawrence T. Pileggi:
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(2): 210-215 (1997) |
| 1996 |
|---|
| 5 | EE | Satyamurthy Pullela,
Noel Menezes,
Lawrence T. Pileggi:
Post-processing of clock trees via wiresizing and buffering for robust design.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(6): 691-701 (1996) |
| 1995 |
|---|
| 4 | EE | Noel Menezes,
Satyamurthy Pullela,
Lawrence T. Pileggi:
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization.
DAC 1995: 690-695 |
| 1994 |
|---|
| 3 | EE | Noel Menezes,
Satyamurthy Pullela,
Florentin Dartu,
Lawrence T. Pillage:
RC interconnect synthesis-a moment fitting approach.
ICCAD 1994: 418-425 |
| 2 | EE | Jessica Qian,
Satyamurthy Pullela,
Lawrence T. Pillage:
Modeling the "Effective capacitance" for the RC interconnect of CMOS gates.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1526-1535 (1994) |
| 1993 |
|---|
| 1 | EE | Satyamurthy Pullela,
Noel Menezes,
Lawrence T. Pillage:
Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization.
DAC 1993: 165-170 |
