| 2004 |
|---|
| 16 | | Prab Varma:
Verification evolution or industrial revolution?
IEEE Design & Test of Computers 21(2): 168- (2004) |
| 2003 |
|---|
| 15 | EE | Prab Varma:
Design Verification Problems: Test To The Rescue?.
ITC 2003: 1292 |
| 2001 |
|---|
| 14 | EE | Magdy S. Abadir,
Scott Davidson,
Vijay Nagasamy,
Dhiraj K. Pradhan,
Prab Varma:
ATPG for Design Errors-Is It Possible?
VTS 2001: 283-285 |
| 1998 |
|---|
| 13 | EE | Bechir Ayari,
Prab Varma:
Test Cycle Count Reduction in a Parallel Scan BIST Environment.
Asian Test Symposium 1998: 21-26 |
| 12 | EE | Prab Varma:
System Chip Test Challenges, Are There Solutions Today? (Panel).
DAC 1998: 750-751 |
| 11 | EE | Prab Varma:
System chip test: are we there yet?
ITC 1998: 1144 |
| 10 | EE | Prab Varma,
Sandeep Bhatia:
A structured test re-use methodology for core-based system chips.
ITC 1998: 294-302 |
| 1997 |
|---|
| 9 | EE | Sandeep Bhatia,
Prab Varma:
Test Compaction in a Parallel Access Scan Environment.
Asian Test Symposium 1997: 300-305 |
| 1996 |
|---|
| 8 | | Sandeep Bhatia,
Tushar Gheewala,
Prab Varma:
A Unifying Methodology for Intellectual Property and Custom Logic Testing.
ITC 1996: 639-648 |
| 7 | EE | Sandeep K. Gupta,
Slawomir Pilarski,
Sudhakar M. Reddy,
Jacob Savir,
Prab Varma:
Delay Fault Testing: How Robust are Our Models?
VTS 1996: 502-503 |
| 1995 |
|---|
| 6 | | Prab Varma:
Optimizing Product Profitability - The Test Way.
ITC 1995: 922 |
| 1994 |
|---|
| 5 | | Prab Varma:
On Path-Delay Testing in a Standard Scan Environment.
ITC 1994: 164-173 |
| 1993 |
|---|
| 4 | | Prab Varma,
Tushar Gheewala:
Delay Testing Using a Matrix of Accessible Storage.
ITC 1993: 243-252 |
| 3 | | Prab Varma:
Scan DFT: Why More Can Cost Less.
ITC 1993: 267 |
| 1987 |
|---|
| 2 | EE | S. B. Tan,
K. Totton,
Keith Baker,
Prab Varma,
R. Porter:
A Fast Signature Simulation Tool for Built-In Self-Testing Circuits.
DAC 1987: 17-25 |
| 1984 |
|---|
| 1 | | Prab Varma,
Anthony P. Ambler,
Keith Baker:
An Analysis of the Economics of Self Test.
ITC 1984: 20-30 |
