Bart Vermeulen

2008
18	EE	Bart Vermeulen, Kees Goossens, Siddharth Umrani: Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip. NOCS 2008: 3-12
2007
17	EE	Udaya Seshua, Nagaraju Bussa, Bart Vermeulen: A Run-Time Memory Protection Methodology. ASP-DAC 2007: 498-503
16	EE	Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek: Communication-Centric SoC Debug Using Transactions. European Test Symposium 2007: 69-76
15	EE	Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek: Transaction-Based Communication-Centric Debug. NOCS 2007: 95-106
2005
14	EE	Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen: Optimal Interconnect ATPG Under a Ground-Bounce Constraint. J. Electronic Testing 21(1): 17-31 (2005)
2004
13	EE	Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel: Automatic generation of breakpoint hardware for silicon debug. DAC 2004: 514-517
12	EE	Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge: Trends in Testing Integrated Circuits. ITC 2004: 688-697
2003
11	EE	Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Müller: Creating Value Through Test. DATE 2003: 10402-10409
10	EE	Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen: Optimal Interconnect ATPG Under a Ground-Bounce Constraint. ITC 2003: 369-378
9	EE	Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts: Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. IEEE Design & Test of Computers 20(2): 8-18 (2003)
2002
8	EE	Sandeep Kumar Goel, Bart Vermeulen: Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. ITC 2002: 1103-1110
7	EE	Bart Vermeulen: TAPS All Over My Chips! So Now What Do I Do? ITC 2002: 1190
6	EE	Bart Vermeulen, Tom Waayers, Sjaak Bakker: EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. ITC 2002: 55-63
5	EE	Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel: Core-Based Scan Architecture for Silicon Debug. ITC 2002: 638-647
4	EE	Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark: Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? VTS 2002: 445-446
3	EE	Bart Vermeulen, Sandeep Kumar Goel: Design for Debug: Catching Design Errors in Digital Chips. IEEE Design & Test of Computers 19(3): 37-45 (2002)
2001
2		Bart Vermeulen, Steven Oostdijk, Frank Bouwman: Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip. ITC 2001: 121-130
1999
1		Gert-Jan van Rootselaar, Bart Vermeulen: Silicon debug: scan chains alone are not enough. ITC 1999: 892-902

Coauthor Index

1	Sjaak Bakker	[6]
2	Martijn T. Bennebroek	[15] [16]
3	Ben Bennetts (R. G. Bennetts)	[9]
4	Frank Bouwman	[2]
5	Nagaraju Bussa	[17]
6	C. J. Clark	[4]
7	Bulent I. Dervisoglu	[4]
8	Sandeep Kumar Goel	[3] [5] [8] [13]
9	Kees G. W. Goossens (Kees Goossens)	[15] [16] [18]
10	Bob Gottlieb	[4]
11	Henk D. L. Hollmann	[9] [10] [14]
12	Camelia Hora	[12]
13	Michael Kessler	[11]
14	Bernd Koenemann	[4]
15	Bram Kruseman	[12]
16	Robert Madge	[11]
17	Erik Jan Marinissen	[9] [10] [11] [12] [14]
18	Michael Müller	[11]
19	Fidel Muradali	[4]
20	Steven Oostdijk	[2]
21	Mike Ricchetti	[4]
22	Robert Van Rijsinge	[12]
23	Gert-Jan van Rootselaar	[1]
24	Udaya Seshua	[17]
25	Remco van Steeden	[15] [16]
26	Siddharth Umrani	[18]
27	Mohammad Zalfany Urfianto	[13]
28	Tom Waayers	[5] [6]

Colors in the list of coauthors