| 2008 |
|---|
| 60 | EE | Bernhard Scholz,
Bernd Burgstaller,
Jingling Xue:
Minimal placement of bank selection instructions for partitioned memory architectures.
ACM Trans. Embedded Comput. Syst. 7(2): (2008) |
| 59 | EE | Minyi Guo,
Jingling Xue:
Advances in high performance computing.
The Journal of Supercomputing 43(2): 105-106 (2008) |
| 58 | EE | Jingling Xue,
Minyi Guo,
Daming Wei:
Improving the parallelism of iterative methods by aggressive loop fusion.
The Journal of Supercomputing 43(2): 147-164 (2008) |
| 2007 |
|---|
| 57 | EE | Lian Li,
Hui Wu,
Hui Feng,
Jingling Xue:
Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation.
Asia-Pacific Computer Systems Architecture Conference 2007: 63-74 |
| 56 | EE | Yi Lu,
John Potter,
Jingling Xue:
Validity Invariants and Effects.
ECOOP 2007: 202-226 |
| 55 | EE | Lei Pan,
Jingling Xue,
Ming Kin Lai,
Michael B. Dillencourt,
Lubomir F. Bic:
Toward Automatic Data Distribution for Migrating Computations.
ICPP 2007: 27 |
| 54 | EE | Lian Li,
Quan Hoang Nguyen,
Jingling Xue:
Scratchpad allocation for data aggregates in superperfect graphs.
LCTES 2007: 207-216 |
| 53 | EE | Xavier Vera,
Björn Lisper,
Jingling Xue:
Data cache locking for tight timing calculations.
ACM Trans. Embedded Comput. Syst. 7(1): (2007) |
| 52 | EE | Lian Li,
Jingling Xue:
Trace-based leakage energy optimisations at link time.
Journal of Systems Architecture 53(1): 1-20 (2007) |
| 51 | EE | Jingling Xue,
Phung Hua Nguyen,
John Potter:
Interprocedural side-effect analysis for incomplete object-oriented software modules.
Journal of Systems and Software 80(1): 92-105 (2007) |
| 2006 |
|---|
| 50 | EE | Lian Li,
Jingling Xue:
Trace-Based Data Cache Leakage Reduction at Link Time.
Asia-Pacific Computer Systems Architecture Conference 2006: 175-188 |
| 49 | EE | Bernhard Scholz,
Bernd Burgstaller,
Jingling Xue:
Minimizing bank selection instructions for partitioned memory architecture.
CASES 2006: 201-211 |
| 48 | EE | Jingling Xue,
Jens Knoop:
A Fresh Look at PRE as a Maximum Flow Problem.
CC 2006: 139-154 |
| 47 | EE | Baoliu Ye,
Minyi Guo,
Jingling Xue:
CoopStream: A Cooperative Cache Based Streaming Schedule Scheme for On-demand Media Services on Overlay Networks.
ICPP 2006: 577-584 |
| 46 | EE | Hui Wu,
Joxan Jaffar,
Jingling Xue:
Instruction Scheduling with Release Times and Deadlines on ILP Processors.
RTCSA 2006: 51-60 |
| 45 | EE | Jingling Xue,
Qiong Cai,
Lin Gao:
Partial dead code elimination on predicated code regions.
Softw., Pract. Exper. 36(15): 1655-1685 (2006) |
| 44 | EE | Jingling Xue,
Qiong Cai:
A lifetime optimal algorithm for speculative PRE.
TACO 3(2): 115-155 (2006) |
| 2005 |
|---|
| 43 | | Thambipillai Srikanthan,
Jingling Xue,
Chip-Hong Chang:
Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings
Springer 2005 |
| 42 | EE | Phung Hua Nguyen,
Jingling Xue:
Interprocedural Side-Effect Analysis and Optimisation in the Presence of Dynamic Class Loading.
ACSC 2005: 9-18 |
| 41 | EE | Canqun Yang,
Xuejun Yang,
Jingling Xue:
Improving the Performance of GCC by Exploiting IA-64 Architectural Features.
Asia-Pacific Computer Systems Architecture Conference 2005: 236-251 |
| 40 | EE | Jingling Xue,
Phung Hua Nguyen:
Completeness Analysis for Incomplete Object-Oriented Programs.
CC 2005: 271-286 |
| 39 | EE | Jingling Xue:
Compiler-Directed Scratchpad Memory Management.
ICESS 2005: 2 |
| 38 | EE | Weng-Long Chang,
Michael (Shan-Hui) Ho,
Minyi Guo,
Xiaohong Jiang,
Jingling Xue,
Minglu Li:
Fast Parallel DNA-Based Algorithms for Molecular Computation: Determining a Prime Number.
ICITA (1) 2005: 447-452 |
| 37 | EE | Jingling Xue,
Qingguang Huang,
Minyi Guo:
Enabling Loop Fusion and Tiling for Cache Performance by Fixing Fusion-Preventing Data Dependences.
ICPP 2005: 107-115 |
| 36 | EE | Lian Li,
Lin Gao,
Jingling Xue:
Memory Coloring: A Compiler Approach for Scratchpad Memory Management.
IEEE PACT 2005: 329-338 |
| 35 | EE | Jingling Xue:
Aggressive Loop Fusion for Improving Locality and Parallelism.
ISPA 2005: 224-238 |
| 34 | EE | Pen-Chung Yew,
Jingling Xue:
Forword.
J. Comput. Sci. Technol. 20(5): 575-576 (2005) |
| 2004 |
|---|
| 33 | | Pen-Chung Yew,
Jingling Xue:
Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings
Springer 2004 |
| 32 | EE | Phung Hua Nguyen,
Jingling Xue:
Strength Reduction for Loop-Invariant Types.
ACSC 2004: 213-222 |
| 31 | EE | Budi Kurniawan,
Jingling Xue:
A Comparative Study of Web Application Design Models Using the Java Technologies.
APWeb 2004: 711-721 |
| 30 | EE | Qiong Cai,
Lin Gao,
Jingling Xue:
Region-Based Partial Dead Code Elimination on Predicated Code.
CC 2004: 150-166 |
| 29 | EE | Lian Li,
Jingling Xue:
A trace-based binary compilation framework for energy-aware computing.
LCTES 2004: 95-106 |
| 28 | EE | Jingling Xue,
Xavier Vera:
Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior.
IEEE Trans. Computers 53(5): 547-566 (2004) |
| 2003 |
|---|
| 27 | EE | Qiong Cai,
Jingling Xue:
Optimal and Efficient Speculation-Based Partial Redundancy Elimination.
CGO 2003: 91-104 |
| 26 | EE | Qingguang Huang,
Jingling Xue,
Xavier Vera:
Code Tiling for Improving the Cache Performance of PDE Solvers.
ICPP 2003: 615- |
| 25 | EE | Xavier Vera,
Björn Lisper,
Jingling Xue:
Data Caches in Multitasking Hard Real-Time Systems.
RTSS 2003: 154-165 |
| 24 | EE | Xavier Vera,
Björn Lisper,
Jingling Xue:
Data cache locking for higher program predictability.
SIGMETRICS 2003: 272-282 |
| 2002 |
|---|
| 23 | EE | Xavier Vera,
Jingling Xue:
Let's Study Whole-Program Cache Behaviour Analytically.
HPCA 2002: 175-186 |
| 22 | EE | Jingling Xue,
Patrick M. Lenders:
Space-Time Equations for Non-Unimodular Mappings.
Int. J. Comput. Math. 79(5): 555 (2002) |
| 21 | EE | Patrick M. Lenders,
Jingling Xue:
Eigenvectors-based parallelisation of nested loops with affine dependences.
Parallel Algorithms Appl. 17(3): 227-248 (2002) |
| 20 | | Jingling Xue,
Wentong Cai:
Time-minimal tiling when rise is larger than zero.
Parallel Computing 28(6): 915-939 (2002) |
| 2000 |
|---|
| 19 | | Jingling Xue:
Loop Tiling for Parallelism
Kluwer 2000 |
| 18 | | Peiyi Tang,
Jingling Xue:
Generating efficient tiled code for distributed memory machines.
Parallel Computing 26(11): 1369-1410 (2000) |
| 1999 |
|---|
| 17 | EE | Shiping Chen,
Jingling Xue:
Partitioning and scheduling loops on NOWs.
Computer Communications 22(11): 1017-1033 (1999) |
| 1998 |
|---|
| 16 | | Jingling Xue,
Chua-Huang Huang:
Reuse-Driven Tiling for Improving Data Locality.
International Journal of Parallel Programming 26(6): 671-696 (1998) |
| 1997 |
|---|
| 15 | | Jingling Xue,
Chua-Huang Huang:
Reuse-Driven Tiling for Data Locality.
LCPC 1997: 16-33 |
| 14 | | Jingling Xue:
Communication-Minimal Tiling of Uniform Dependence Loops.
J. Parallel Distrib. Comput. 42(1): 42-59 (1997) |
| 13 | | Jingling Xue:
Unimodular Transformations of Non-Perfectly Nested Loops.
Parallel Computing 22(12): 1621-1645 (1997) |
| 12 | | Jingling Xue:
On Tiling as a Loop Transformation.
Parallel Processing Letters 7(4): 409-424 (1997) |
| 1996 |
|---|
| 11 | EE | Jingling Xue:
Affine-by-Statement Transformations of Imperfectly Nested Loops.
IPPS 1996: 34-38 |
| 10 | | Jingling Xue:
Communication-Minimal Tiling of Uniform Dependence Loops.
LCPC 1996: 330-349 |
| 9 | | Jingling Xue:
Transformations of Nested Loops with Non-Convex Iteration Spaces.
Parallel Computing 22(3): 339-368 (1996) |
| 1995 |
|---|
| 8 | EE | Jingling Xue:
Constructing DO loops for non-convex iteration spaces in compiling for parallel machines.
IPPS 1995: 364-368 |
| 1994 |
|---|
| 7 | | Jingling Xue,
Patrick M. Lenders:
Avoiding Data Link and Computational Conflicts in Mapping Nested Loop Algorithms to Lower-Dimensional Processor Arrays.
ICPADS 1994: 567-572 |
| 6 | | Jingling Xue:
Automating Non-Unimodular Loop Transformations for Massive Parallelism.
Parallel Computing 20(5): 711-728 (1994) |
| 1993 |
|---|
| 5 | | Jingling Xue:
An Algorithm to Automate Non-Unimodular Transformations of Loop Nests.
SPDP 1993: 512-521 |
| 1992 |
|---|
| 4 | | Jingling Xue:
On the Loading, Recovery and Access of Stationary Data in Systolic Arrays.
CONPAR 1992: 259-264 |
| 1991 |
|---|
| 3 | | Jingling Xue,
Christian Lengauer:
Specifying control signals for one-dimensional systolic arrays by uniform recurrence equations.
Algorithms and Parallel VLSI Architectures 1991: 181-186 |
| 2 | | Jingling Xue:
Specifying control signals for Systolic Arrays by Uniform Recurrence Equations.
Parallel Processing Letters 1: 83-93 (1991) |
| 1988 |
|---|
| 1 | EE | Jingling Xue,
Xian-Long Hong:
A new data structure for representing cell hierarchy in layout design.
Computers & Graphics 12(3-4): 341-348 (1988) |
