IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 1

Volume 1, Number 1, January 1982

• Marvin E. Daniel, Charles W. Gwyn:
  CAD Systems for IC Design. 2-12
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• Luís M. Vidigal, Stephen W. Director:
  A Design Centering Algorithm for Nonconvex Regions of Acceptability. 13-24
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• Takeshi Yoshimura, Ernest S. Kuh:
  Efficient Algorithms for Channel Routing. 25-35
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• Hal W. Daseking, Robert I. Gardner, Paul B. Weil:
  VISTA: A VLSI CAD System. 36-52
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Volume 1, Number 2, April 1982

• Gio Wiederhold, Anne F. Beetem, Garrett E. Short:
  A Database Approach to Communication in VLSI Design. 57-63
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• Gary D. Hachtel, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
  An Algorithm for Optimal PLA Folding. 63-77
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• A. Schütz, Siegfried Selberherr, Hans W. Pötzl:
  Analysis of Breakdown Phenomena in MOSFET's. 77-85
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• Walter L. Engl, Rainer Laur, Heinz K. Dirks:
  MEDUSA - A Simulator for Modular Circuits. 85-93
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• M. Latif, P. R. Bryant:
  Network Analysis Approach to Multidimensional Modeling of Transistors Including Thermal Effects. 94-101
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Volume 1, Number 3, July 1982

• C. J. Hage, Ronald A. Rohrer:
  Efficient Op Amp Circuit Analysis with Manufacturer Specified Macromodel Parameters. 105-112
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• Dileep A. Divekar, R. E. Lovelace:
  Modeling of avalanche generation current of bipolar junction transistors for computer circuit simulation. 112-116
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• Francis B. Grosz, Timothy N. Trick:
  Some Modifications to Newton's Method for the Determination of the Steady-State Response of Nonlinear Oscillatory Circuits. 116-120
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• Wojciech Maly, Andrzej J. Strojwas:
  Statistical Simulation of the IC Manufacturing Process. 120-131
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• Ekachai Lelarasmee, Albert E. Ruehli, Alberto L. Sangiovanni-Vincentelli:
  The Waveform Relaxation Method for Time-Domain Analysis of Large Scale Integrated Circuits. 131-145
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Volume 1, Number 4, October 1982

• G. W. Taylor, Wolfgang Fichtner, J. G. Simmons:
  A Description of MOS Internodal Capacitances for Transient Simulations. 150-156
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• Donald B. Estreich, Robert W. Dutton:
  Modeling Latch-Up in CMOS Integrated Circuits. 157-162
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• D. E. Ward, K. Doganis:
  Optimized Extraction of MOS Model Parameters. 163-168
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• Ping Yang, Pallab K. Chatterjee:
  SPICE Modeling for Small Geometry MOSFET Circuits. 169-182
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• J. Mar, Sheau-Suey Li, Swei-Yam Yu:
  Substrate Current Modeling for Circuit Simulation. 183-186
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• D. C. Schmidt:
  Circuit Pack Parameter Estimation Using Rent's Rule. 186-192
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• Martin E. Newell, Daniel T. Fitzpatrick:
  Exploitation of Hierarchy in Analyses of Integrated Circuit Artwork. 192-200
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• Andrew W. Nagle, Richard J. Cloutier, Alice C. Parker:
  Synthesis of Hardware for the Control of Digital Systems. 201-212
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• A. R. Teene, Mohamed I. Elmasry, David J. Roulston:
  WATPC: A Computer-Aided Design Package for Digital Bipolar Integrated Circuits. 213-219
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