ISCA92: Table of contents

Zucker, R. N.; Baer, J.-L.: A Performance Study of Memory Consistency Models. 2-12.

Keleher, P.; Cox, A. L.; Zwaenepoel, W.: Lazy Release Consistency for Software Distributed Shared Memory. 13-21.

Gharachorloo, K.; Gupta, A.; Hennessy, J.: Hiding Memory Latency using Dynamic Scheduling in Shared-Memory Multiprocessors. 22-35.

Fernandes, E. S. T.; Barbosa, F. M. B.: Effects of Building Blocks on the Performance of Super-Scalar Architectures. 36-45.

Lam, M. S.; Wilson, R. P.: Limits of Control Flow on Parallelism. 46-57.

Franklin, M.; Sohi, G. S.: The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism. 58-69.

Litaize, D.; Mzoughi, A.; Rochange, C.; Sainrat, P.: Towards a Shared-Memory Massively Parallel Multiprocessor. 70-79.

Stenström, P.; Joe, T.; Gupta, A.: Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures. 80-91.

Lenoski, D.; Laudon, J.; Joe, T.; Nakahira, D.; Stevens, L.; Gupta, A.; Hennessy, J.: The DASH Prototype: Implementation and Performance. 92-105.

Intrater, G.; Spillinger, I.: Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers. 106-113.

Chen, J. B.; Borg, A.; Jouppi, N. P.: A Simulation Based Study of TLB Performance. 114-123.

Yeh, T.-Y.; Patt, Y. N.: Alternative Implementations of Two-Level Adaptive Branch Prediction. 124-135.

Hirata, H.; Kimura, K.; Nagamine, S.; Mochizinki, Y.; Nishimura, A.; Nakase, Y.; Nishizawa, T.: An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads. 136-145.

Sato, M.; Kodama, Y.; Sakai, S.; Yamaguchi, Y.; Koumura, Y.: Thread-based Programming for the EM-4 Hybrid Dataflow Machine. 146-155.

Nikhil, R. S.; Papadopoulos, G. M.; Arvind, G.: \astT: A Multithreaded Massively Parallel Architecture. 156-169.

Dubnicki, C.; LeBlanc, T. J.: Adjustable Block Size Coherent Caches. 170-180.

Olukotun, K.; Mudge, T.; Brown, R.: Performance Optimization of Pipelined Primary Caches. 181-190.

McFarling, S.: Cache Replacement with Dynamic Exclusion. 191-201.

Keckler, S. W.; Dally, W. J.: Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism. 202-213.

Soothe, B.; Ranade, A.: Improved Multithreading Techniques for Hiding Communication Latency in Multiprocessor. 214-223.

DeGloria, A.; Faraboschi, P.: Instruction-level Parallelism in Prolog: Analysis and Architectural Support. 224-235.

Kurian, L.; Hulina, P. T.; Coraor, L. D.: Memory Latency Effects in Decoupled Architectures with a Single Data Memory Module. 236-245.

Seznec, A.; Lenfant, J.: Interleaved Parallel Schemes: Improved Memory Throughput on Supercomputers. 246-255.

von Eicken, T.; Culler, D. E.; Goldstein, S. C.; Schauser, K. E.: Active Messages: A Mechanism for Integrated Communication and Computation. 256-267.

Chien, A. A.; Kim, J. H.: Planar-Adaptive Routing: Low-cost Adaptive Networks for Multiprocessors. 268-277.

Glass, C. J.; Ni, L. M.: The Turn Model for Adaptive Routing. 278-287.

Shimizu, T.; Horie, T.; Ishihata, H.: Low-Latency Message Communication Support for the AP1000. 288-299.

Aichinger, B. P.: Futurbus+ as an I/O Bus: Profile B. 300-307.

Reddy, A. L. N.: A Study of I/O System Organizations. 308-317.

Menon, J.; Mattson, D.: Comparison of Sparing Alternatives for Disk Arrays. 318-331.

Siegle, M.; Hofmann, R.: Monitoring Program Behaviour on SUPRENUM. 332-341.

Austin, T. M.; Sohi, G. S.: Dynamic Dependency Analysis of Ordinary Programs. 342-351.

Najjar, W. A.; Miller, W. M.; Böhm, A. P. W.: An Analysis of Loop Latency in Dataflow Execution. 352-361.

Yang, Q.; Yang, L. W.: A Novel Cache Design for Vector Processing. 362-371.

Valero, M.; Lang, T.; Llabería, J. M.; Peiron, M.; Ayguadé, E.; Navarro, J. J.: Increasing the Number of Strides for Conflict-Free Vector Access. 372-381.

Wulf, W. A.: Evaluation of the WM Architecture. 382-391.

Johnson, K. L.: The Impact of Communication Locality on Large-Scale Multiprocessor Performance. 392-402.

Scott, S. L.; Goodman, J. R.; Vernon, M. K.: Performance of the SCI Ring. 403-414.

Talluri, M.; Kong, S.; Hill, M. D.; Patterson, D. A.: Tradeoffs in Supporting Two Page Sizes. 415-426.

Seznec, A.; Courtel, K.: OPAC: A Floating-Point Coprocessor Dedicated to Compute-Bound Kernels. 427-427.

Louri, A.; Na, J.: Parallel Electro-Optical Rule-Based System for Fast Execution of Expert Systems. 427-427.

Louri, A.; Sung, H.: A New Compiler-Directed Cache Coherence Scheme for Shared Memory Multiprocessors with Fast and Parallel Explicit Invalidation. 428-428.

Cheng, D.-C.; Ghose, K.: The Time-Constrained Barrier Synchronizer and Its Applications in Parallel Systems. 428-428.

Singh, G. B.: Architecture of a Graphics Processor. 429-429.

Yomtov, R.: Performance Evaluation of Disk Subsystems. 429-429.

Sklenar, I.: Prefetch Unit for Vector Operations on Scalar Computers. 430-430.

Lai, F.; Chang, M.-C.: Enhancing Boosting with Semantic Register in a Superscalar Processor. 430-430.

Uht, A. K.; Johnson, D. B.: Data Path Issues in a Highly Concurrent Machine. 431-431.

Newman, G.: Memory Management Support for Tiled Array Organization. 431-431.

Sayeed, M. A.; Atiqazzaman, M.: Performance of Multiple-Bus Multiprocessor Under Non-Uniform Memory Reference Model. 432-432.

Fineberg, S. A.; Casavant, T. L.; Pease, B. H.: Seamless - A Latency-Tolerant RISC-Based Multiprocessor Architecture. 432-432.

Varma, A.; Sinha, G.: A Class of Prefetch Schemes for On-Chip Data Caches. 433-432.

Kechadi, M. T.; Dekeyser, J.-L.; Marquet, P.; Preux, P.: Performance Improvement for Vector Pipeline Multiprocessor Systems Using a Disordered Execution Model. 433-433.

Abnous, A.; Bagherzadeh, N.: Pipelining and Bypassing in a VLIW Processor. 434-434.

Prakash, S.; Parker, A. C.: Synthesis of Application-Specific Heterogeneous Multiprocessor Systems. 434-434.

Farrens, M.; Park, A.; Fanfelle, R.; Ng, P.; Tyson, G.: A Partitioned Translation Lookaside Buffer Approach to Reducing Address Bandwidth. 435-435.

Laudon, J.; Gupta, A.; Horowitz, M.: Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors. 435-435.

Singh, J. P.: Implications of Hierarchical N-body Methods for Multiprocessor Architecture. 436-436.

Alleyne, B. D.; Scherson, I. D.: Expanded Delta Networks for Very Large Parallel Computers. 436-436.

Michael, W.: Directory-Based Cache Coherency Protocol for a Ring-Connected Multiprocessor-Array. 437-437.

Lai, K.; Wang, W.-H.; Quinlan, J.: Revisit The Case For Direct-Mapped Caches: A Case for Two-Way Set-Associative Level-Two Caches. 437-437.

Culler, D. E.; Gunter, M.; Lee, J. C.: Analysis of Multithreaded Microprocessors under Multiprogramming. 438-438.

Wittenbrink, C. M.; Somani, A. K.; Chen, C. H.: Cache Write Generate for High Performance Parallel Processing. 438-438.

Burkhardt, W. H.; Rust, S.: Integrated Computer Architecture Development System. 439-439.