ISCA93: Table of contents

Cypher, R.; Ho, A.; Konstantinidou, S.; Messina, P.: Architectural Requirements of Parallel Scientific Applications with Explicit Communication. 2-13.

Rothberg, E.; Singh, J. P.; Gupta, A.: Working Sets, Cache Sizes, and Node Granularity Issues for Large-Scale Multiprocessors. 14-26.

Nagle, D.; Uhlig, R.; Stanley, T.; Sechrest, S.; Mudge, T.; Brown, R.: Design Tradeoffs for Software-Managed TLBs. 27-38.

Huck, J.; Hays, J.: Architectural Support for Translation Table Management in Large Address Space Machines. 39-51.

Cao, P.; Lim, S. B.; Venkataraman, S.; Wilkes, J.: The TickerTAIP Parallel RAID Architecture. 52-63.

Stodolsky, D.; Gibson, G.; Holland, M.: Parity Logging Overcoming the Small Write Problem in Redundant Disk Arrays. 64-75.

Menon, J.; Cortney, J.: The Architecture ofa Fault-Tolerant Cached RAID Controller. 76-87.

Dubois, M.; Skeppstedt, J.; Ricciulli, L.; Ramamurthy, K.; Stenström, P.: The Detection and Elimination of Useless Misses in Multiprocessors. 88-97.

Cox, A. L.; Fowler, R. J.: Adaptive Cache Coherency for Detecting Migratory Shared Data. 98-108.

Stenström, P.; Brorsson, M.; Sandberg, L.: An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing. 109-119.

Waldspurger, C. A.; Weihl, W. E.: Register Relocation: Flexible Contexts for Multithreading. 120-130.

Hidaka, Y.; Koihe, H.; Tanaka, H.: Multiple Threads in Cyclic Register Windows. 131-143.

Dwarkadas, S.; Keleher, P.; Cox, A. L.; Zwaenepoel, W.: Evaluation of Release Consistent Software Distributed Shared Memory on Emerging Network Technology. 144-155.

Wood, D. A.; Chandra, S.; Falsafi, B.; Hill, M. D.; Larus, J. R.; Lebeck, A. R.; Lewis, J. C.; Mukherjee, S. S.; Palacharla, S.; Reinhardt, S. K.: Mechanisms for Cooperative Shared Memory. 156-168.

Seznec, A.: A Case for Two-Way Skewed-Associative Caches. 169-178.

Agarwal, A.; Pudar, S. D.: Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches. 179-190.

Jouppi, N. P.: Cache Write Policies and Performance. 191-202.

Boyd, E. L.; Davidson, E. S.: Hierarchical Performance Modeling with MACS: A Case Study of the Convex C-240. 203-212.

Kuck, D.; Davidson, E.; Lawrie, D.; Sameh, A.; Zhu, C.-Q.; Veidenbaum, A.; Konicek, J.; Yew, P.; Gallivan, K.; Jalby, W.; Wijshoff, H.; Bramley, R.; Yang, U. M.; Emrath, P.; Padua, D.; Eigenmann, R.; Hoeflinger, J.; Jaxon, G.; Li, Z.; Murphy, T.; Andrews, J.; Turner, S.: The Cedar System and an Initial Performance Study. 213-223.

Noakes, M. D.; Wallach, D. A.; Dally, W. J.: The J-Machine Multicomputer: An Architectural Evaluation. 224-236.

Bunda, J.; Fussell, D.; Jenevein, R.; Athas, W. C.: 16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors. 237-246.

Kiyohara, T.; Mahlke, S.; Chen, W.; Bringmann, R.; Hank, R.; Anik, S.; Hwu, W.-M.: Register Connection: A New Approach to Adding Registers into Instruction Set Architectures. 247-256.

Yeh, T.-Y.; Patt, Y. N.: A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History. 257-267.

Barroso, L. A.; Dubois, M.: The Performance of Cache-Coherent Ring-Based Multiprocessors. 268-277.

Tullsen, D. M.; Eggers, S. J.: Limitations of Cache Prefetching on a Bus-Based Multiprocessor. 278-288.

Herlihy, M.; Moss, J. E. B.: Transactional Memory: Architectural Support for Lock-Free Data Structures. 289-301.

Spertus, E.; Goldstein, S. C.; Schauser, K. E.; von Eicken, T.; Culler, D. E.; Dally, W. J.: Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5. 302-313.

Horie, T.; Hayashi, K.; Shimizu, T.; Ishihata, H.: Improving AP1000 Parallel Computer Performance with Message Communication. 314-326.

Hsu, W.-C.; Smith, J. E.: Performance of Cached DRAM Organizations in Vector Supercomputers. 327-336.

Gao, Q. S.: The Chinese Remainder Theorem and the Prime Memory System. 337-340.

Seznec, A.; Lenfant, J.: Odd Memory Systems May Be Quite Interesting. 341-350.

Boppana, R. V.; Chalasani, S.: A Comparison of Adaptive Wormhole Routing Algorithms. 351-360.